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\title{Cheko: high-density electrode driver for scalable ion-trap quantum computing}
\date{December 7, 2020}

\begin{document}
\maketitle

\section{Background}
Quantum computing experiments with trapped ions need an increasing number of electrodes when scaling up their number of qubits, for the purposes of ion shuttling (as required to implement many quantum gate schemes) and compensating stray electric fields (which decrease the fidelity of operations).

An example of an ion trap with a large number of electrodes is the NIST microfabricated ``racetrack'' ion trap\cite{racetrack}, with 150 trapping zones, which was used to demonstrate transport of atomic ions between the legs of a ‘Y’-type junction, as well as the use of a basic component design library that can be quickly assembled to form structures optimized for a particular experiment.

\begin{figure}[h]
\centering
\includegraphics[width=0.8\textwidth]{racetrack_ion_trap.jpg}
\caption{The ``racetrack'' ion trap, measuring a few millimeters. Credits: J.Amini/NIST}
\end{figure}

Ion traps operate in a ultra-high vacuum environment, while control signals originate from the laboratory at atmospheric pressure. Directly accessing all the electrodes from the ion trap from the laboratory requires electrical connections between vacuum and atmosphere sides (``vacuum feedthroughs'').  They are costly and a potential source of vacuum leaks that cause malfunction of the entire apparatus requiring weeks or months of repair. Furthermore, cabling on both vacuum and atmosphere sides becomes difficult and a potential source of signal integrity problems. Due to all these issues, in the NIST racetrack\cite{racetrack} ion trap, only 48 electrical potentials could be controlled, with groups of the 150 electrodes sharing one potential. The authors nevertheless suggested repeating the hexagonal pattern of the structure as a way to scale the design to higher number of qubits -- which would be problematic with typical vacuum chamber and control system design.

Transport waveforms for ions are commonly generated by a spline interpolator\cite{pdq} using digital signal processing, and a CIC interpolator could also be used. The amount of bandwidth required to determine a spline waveform is much less than the bandwidth of the resulting waveform. Therefore, it can be seen as wasteful to consume expensive vacuum feedthrough bandwidth by transferring the ``uncompressed'' waveform instead of the more compact spline (or CIC) representation.

This document proposes moving the interpolator, DAC, and electrode driver closer to the ion trap, on the vacuum side, thereby optimizing use of the available vacuum feedthrough bandwidth and alleviating cabling issues. A new device, codenamed ``Cheko'', would be placed next to the trap electrodes, receive bandwidth-optimized digital control commands from an external control system in the laboratory, and drive the trap electrodes.

\section{Architecture}
A low-pin-count digital interface going over the vacuum feedthrough, exposing the Cheko devices to the external control system, carries commands that program the trap electrode voltages. A command consists in a timestamp, channel number, and interpolator data. Commands are buffered inside the device until their respective timestamps are reached, at which point the interpolator data is sent into the corresponding channel. The Cheko devices contain a timestamp counter and a means of synchronizing it with the external control system via a special command. The interpolator continuously generates high-bandwidth data for its DAC channel based on the received data. The interpolator is based on cascaded integrator-comb (CIC) filters. The output of the DAC is amplified to drive its trap electrode.

In order to save the maximum amount of pins, the master device is responsible for avoiding buffer overflows by keeping track of the buffer space available in Cheko devices and the timestamps issued, without the Cheko devices returning backpressure information. A simple status line is used to report errors such as violations of this scheme.

Several Cheko devices can be placed in one vacuum chamber, and share certain pins such as the electrical power supply pins, the clock signal, the status line, and even the data pins if an addressing scheme is implemented.

\begin{figure}[h]
\centering
\begin{tikzpicture}[every text node part/.style={align=center},node distance=3cm]
    \node (begin) [coordinate] {};
    \node [draw, right of=begin, fill=blue!20, minimum height=20em] (evbuf) {Event \\ buffer \\ and \\ Timestamp \\ counter};
    \node [twoportshape, right of=evbuf, yshift=8em, fill=blue!20, t=Interp] (interp0) {};
    \node [twoportshape, right of=evbuf, yshift=4em, fill=blue!20, t=Interp] (interp1) {};
    \node [right of=evbuf, yshift=0em] (interpc) {$\vdots$};
    \node [twoportshape, right of=evbuf, yshift=-8em, fill=blue!20, t=Interp] (interpn) {};
    \node [dacshape, right of=interp0, fill=blue!20] (dac0) {};
    \node [dacshape, right of=interp1, fill=blue!20] (dac1) {};
    \node [dacshape, right of=interpn, fill=blue!20] (dacn) {};
    \node [ampshape, right of=dac0, fill=blue!20] (amp0) {};
    \node [ampshape, right of=dac1, fill=blue!20] (amp1) {};
    \node [ampshape, right of=dacn, fill=blue!20] (ampn) {};
    \node (end0) [coordinate, right of=amp0] {};
    \node (end1) [coordinate, right of=amp1] {};
    \node (endn) [coordinate, right of=ampn] {};

    \draw [->] ([yshift=4em]begin.east) -- node [above] {clock} ([yshift=4em]evbuf.west);
    \draw [->] ([yshift=0em]begin.east) -- node [above] {cmd data} ([yshift=0em]evbuf.west);
    \draw [->] ([yshift=-4em]evbuf.west) -- node [above] {status} ([yshift=-4em]begin.east);

    \draw [->] ([yshift=8em]evbuf.east) -- (interp0);
    \draw [->] ([yshift=4em]evbuf.east) -- (interp1);
    \draw [->] ([yshift=-8em]evbuf.east) -- (interpn);

    \draw [->] (interp0) -- (dac0);
    \draw [->] (interp1) -- (dac1);
    \draw [->] (interpn) -- (dacn);

    \draw [->] (dac0) -- (amp0);
    \draw [->] (dac1) -- (amp1);
    \draw [->] (dacn) -- (ampn);

    \draw [->] (amp0) -- node [above] {to electrode 0} (end0);
    \draw [->] (amp1) -- node [above] {to electrode 1} (end1);
    \draw [->] (ampn) -- node [above] {to electrode n} (endn);
\end{tikzpicture}
\caption{Block diagram of the Cheko device.}
\end{figure}

\section{Specifications}
\subsection{Electrical}
\begin{itemize}
\itemsep0em 
\item Voltage: $\pm$5V to $\pm$10V. This is a requirement from the physics of surface ion traps.
\item Permissible output capacitance: 5pF (TBC). The trap electrode and its connection to the driver are modeled by a capacitor.
\item Sample rate: 10MHz to 100MHz.
\item Slew rate: 100V/$\mu$s (TBC).
\item Current drive capability: 500$\mu$A (TBC) per channel. Derived from permissible output capacitance and slew rate.
\item Number of channels: 30 to 100.
\end{itemize}

\subsection{Size}
The electrode area of the racetrack ion trap\cite{racetrack} with its 150 regions only measures 2x4mm. For a scalable control system, the amount of space used by the electronics that drives these 150 regions must not be significantly larger; or wiring eventually becomes intractable again. From this, it becomes clear that custom ASIC technology is an interesting candidate. It will remain a challenging goal: as a ballpark estimate of the size required, the AD5592R 8-channel DAC is offered by Analog Devices in bare die form measuring 2x2mm. Nevertheless, even if a size of 2x4mm for 150 channels is not achieved, a miniature local electrode control system would be a significant improvement over the systems currently used.

\begin{figure}[h]
\centering
\begin{tikzpicture}
\draw[draw=none, pattern=north east lines, pattern color=gray!40] (5.5,2) rectangle (7.5,2.5) node[anchor=south,pos=.5] {Trapping area};
\filldraw[black] (6,2.25) circle (1pt);
\filldraw[black] (6.25,2.25) circle (1pt);
\filldraw[black] (6.5,2.25) circle (1pt);
\filldraw[black] (6.75,2.25) circle (1pt);
\filldraw[black] (7,2.25) circle (1pt);
\draw[fill=yellow!50] (0,1) rectangle (13,2) node[pos=.5] {Surface-electrode ion trap, shield, and signal routing using through-wafer vias};
\draw[fill=cyan!50] (1,0) rectangle (4,1) node[pos=.5] {Cheko device \#1};
\draw[fill=cyan!50] (5,0) rectangle (8,1) node[pos=.5] {Cheko device \#2};
\draw[fill=cyan!50] (9,0) rectangle (12,1) node[pos=.5] {Cheko device \#3};
\draw[pattern=north west lines, pattern color=gray!40] (0,-2) rectangle (13,0) node[pos=.5] {Heatsink};
\end{tikzpicture}
\caption{Cheko devices could be placed between the ion trap and a heatsink, using flip-chip mounting.}
\end{figure}

\subsection{Temperature range}
Some, but not all, ion trap experiments are done in a cryostat, in particular to reduce ion heating rates and improve vacuum\cite{cryo} (in terms of both pumping speed and ultimate pressure achieved). To address a wider range of ion trap experiments, it is desirable that the device be operable at low temperatures (3 to 15K) as well as room temperature.

\subsection{Vacuum}
The device must be operable in a ultra-high vacuum environment. It must not outgas and must have a sufficient means of dissipating the heat it generates, such as being mounted to the wall of the vacuum chamber acting as heatsink.

\section{Ecosystem and integration}
Cheko will be compatible with the popular ARTIQ\cite{artiq} control and data acquisition system, and will be part of the Sinara\cite{sinara} hardware family. A simple interface module, in the EEM form factor, connects the digital signals of one or several Cheko devices to the FPGA of carrier cards such as Kasli or Kasli-SoC.

\begin{figure}[h]
\centering
\includegraphics[width=0.6\textwidth]{sinara_crate.jpg}
\caption{A Sinara crate with a Kasli FPGA carrier (left) and various modules in the EEM form factor.}
\end{figure}

Since Cheko devices already contain time-tracking logic, they operate as simplified DRTIO leaf nodes. RTIO commands originating from ARTIQ kernels are serialized by gateware inside the FPGA carrier card and transmitted to the Cheko devices via the EEM cable, adapter card, and cable between the vacuum chamber and the Sinara crate.

\begin{thebibliography}{9}
\bibitem{racetrack}
J.M. Amini, H. Uys, J.H. Wesenberg, S. Seidelin, J. Britton, J.J. Bollinger, D. Leibfried, C. Ospelkaus, A.P. VanDevender and D.J. Wineland. 
\textit{Toward scalable ion traps for quantum information processing.} 
New Journal of Physics. March 16, 2010.

\bibitem{pdq}
R. Bowler, U. Warring, J. W. Britton, B. C. Sawyer and J. Amini. 
\textit{Arbitrary waveform generator for quantum information processing with trapped ions.}
Rev. Sci. Instrum. 84, 033108, 2013.

\bibitem{cryo}
M. Niedermayr, R. Blatt.
\textit{Cryogenic surface ion traps.}
Dissertation. \url{https://quantumoptics.at/images/publications/dissertation/niedermayr_diss.pdf}

\bibitem{artiq}
S. Bourdeauducq, R. Jördens, D. Nadlinger, T. Harty, D. Slichter, C. Ballance, J. Lam, S. Maka, E. Wodey, H. Ho, J. W. Britton, P. Kulik, M. Weber, A. Risinger, C. Baynham, P. Zotov, F. Kemarrec and Y. Sionneau.
\textit{ARTIQ: Advanced Real-Time Infrastructure for Quantum physics.}
\url{https://m-labs.hk/artiq/}

\bibitem{sinara}
G. Kasprowicz, P. Kulik, M. Gaska, T. Przywozki, K. Pozniak, J. Jarosinski, J. W. Britton, T. Harty, C. Ballance, W. Zhang, D. Nadlinger, D. Slichter, D. Allcock, S. Bourdeauducq, R. Jördens and K. Pozniak.
\textit{ARTIQ and Sinara: Open Software and Hardware Stacks for Quantum Physics.}
Quantum 2.0 2020, Washington DC, United States.

\end{thebibliography}

\end{document}
