mirror of https://github.com/m-labs/artiq.git
49 lines
1.0 KiB
Python
49 lines
1.0 KiB
Python
eem_fmc_connections = {
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0: [0, 8, 2, 3, 4, 5, 6, 7],
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1: [1, 9, 10, 11, 12, 13, 14, 15],
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2: [17, 16, 24, 19, 20, 21, 22, 23],
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3: [18, 25, 26, 27, 28, 29, 30, 31],
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}
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fmcdio_shiftreg_permutation = [
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1, 0, 3, 2, 5, 4, 7, 6,
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9, 8, 11, 10, 13, 12, 15, 14,
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17, 16, 19, 18, 21, 20, 23, 22,
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25, 24, 27, 26, 29, 28, 31, 30
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]
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def shiftreg_bits(eem, out_pins):
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r = 0
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for i in range(8):
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if i not in out_pins:
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lvds_line = eem_fmc_connections[eem][i]
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shift = fmcdio_shiftreg_permutation.index(lvds_line)
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r |= 1 << shift
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return r
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dio_bank0_out_pins = set(range(4))
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dio_bank1_out_pins = set(range(4, 8))
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urukul_out_pins = {
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0, # clk
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1, # mosi
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3, 4, 5, # cs_n
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6, # io_update
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7, # dds_reset
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}
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urukul_out_pins_aux = {
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4, # sw0
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5, # sw1
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6, # sw2
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7, # sw3
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}
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zotino_out_pins = {
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0, # clk
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1, # mosi
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3, 4, # cs_n
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5, # ldac_n
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7, # clr_n
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}
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