mirror of https://github.com/m-labs/artiq.git
11 lines
300 B
Python
11 lines
300 B
Python
from migen import *
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.wrpll.si549 import Si549
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class WRPLL(Module, AutoCSR):
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def __init__(self, main_dcxo_i2c, helper_dxco_i2c):
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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