mirror of https://github.com/m-labs/artiq.git
135 lines
4.9 KiB
Python
135 lines
4.9 KiB
Python
from migen import *
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from migen.genlib.io import (DifferentialOutput, DifferentialInput,
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DDROutput, DDRInput)
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from artiq.gateware.rtio import rtlink
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class SerDes(Module):
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# crc-12 telco: 0x80f
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def __init__(self, n_data=8, t_clk=7, d_clk=0b1100011,
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n_frame=14, n_crc=12, poly=0x80f):
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"""DDR fast link.
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* One word clock lane with `t_clk` period.
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* Multiple data lanes at DDR speed.
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* One return data lane at slower speed.
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* n_frame//2 - 1 marker bits are used to provide framing.
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* `n_data` lanes
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* `t_clk` bits per clk cycle with pattern `d_clk`
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* `n_frame` words per frame
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* `n_crc` CRC bits per frame for divisor poly `poly`
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"""
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# pins
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self.data = [Signal(2, reset_less=True) for _ in range(n_data)]
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n_mosi = n_data - 2 # mosi lanes
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n_word = n_mosi*t_clk # bits per word
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t_frame = t_clk*n_frame # frame duration
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n_marker = n_frame//2 + 1
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n_body = n_word*n_frame - n_marker - n_crc
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t_miso = 0 # miso sampling latency TODO
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assert n_crc % n_mosi == 0
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# frame data
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self.payload = Signal(n_body)
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# readback data
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self.readback = Signal(n_frame, reset_less=True)
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# data load synchronization event
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self.stb = Signal()
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# # #
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self.submodules.crca = LiteEthMACCRCEngine(
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data_width=n_mosi, width=n_crc, polynom=poly)
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self.submodules.crcb = LiteEthMACCRCEngine(
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data_width=n_mosi, width=n_crc, polynom=poly)
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words_ = []
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j = 0
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# build from LSB to MSB because MSB first
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for i in range(n_frame): # iterate over words
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if i == 0: # data and checksum
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words_.append(C(0, n_crc))
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k = n_word - n_crc
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elif i == 1: # marker
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words_.append(C(1))
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k = n_word - 1
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elif i < n_frame//2 + 2: # marker
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words_.append(C(0))
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k = n_word - 1
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else: # full word
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k = n_word
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# append corresponding frame body bits
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words_.append(self.payload[j:j + k])
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j += k
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words_ = Cat(words_)
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assert len(words_) == n_frame*n_word
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words = Signal(len(words_))
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self.comb += words.eq(words_)
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clk = Signal(t_clk, reset=d_clk)
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i = Signal(max=t_frame//2)
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# big shift register for mosi and
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sr = [Signal(t_frame, reset_less=True) for i in range(n_mosi)]
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assert len(Cat(sr)) == len(words)
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crc_insert = ([d[1] for d in self.data[:-1]] +
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[d[0] for d in self.data[:-1]])
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crc_insert = Cat(crc_insert[-n_crc:])
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miso_sr = Signal(t_frame, reset_less=True)
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miso_sr_next = Signal.like(miso_sr)
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self.comb += [
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self.stb.eq(i == t_frame//2 - 1),
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# LiteETHMACCRCEngine takes data LSB first
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self.crca.data.eq(Cat([sri[-1] for sri in sr[::-1]])),
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self.crcb.data.eq(Cat([sri[-2] for sri in sr[::-1]])),
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self.crcb.last.eq(self.crca.next),
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miso_sr_next.eq(Cat(self.data[-1], miso_sr)),
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# unload miso
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# TODO: align to marker
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self.readback.eq(Cat([miso_sr_next[t_miso + i*t_clk]
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for i in range(n_frame)])),
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]
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self.sync.rio_phy += [
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# shift everything by two bits
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[di.eq(sri[-2:]) for di, sri in zip(self.data, [clk] + sr)],
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clk.eq(Cat(clk[-2:], clk)),
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[sri.eq(Cat(C(0, 2), sri)) for sri in sr],
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miso_sr.eq(miso_sr_next),
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self.crca.last.eq(self.crcb.next),
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i.eq(i + 1),
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If(self.stb,
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i.eq(0),
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clk.eq(clk.reset),
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self.crca.last.eq(0),
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# transpose, load
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[sri.eq(Cat(words[i::n_mosi])) for i, sri in enumerate(sr)],
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# inject crc for the last cycle
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crc_insert.eq(self.crca.next if n_crc // n_mosi == 1
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else self.crcb.next),
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),
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]
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class SerInterface(Module):
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def __init__(self, pins, pins_n):
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self.data = [Signal(2) for _ in range(2 + len(pins.mosi))]
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for d, pp, pn in zip(self.data,
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[pins.clk] + list(pins.mosi),
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[pins_n.clk] + list(pins_n.mosi)):
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ddr = Signal()
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self.specials += [
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# d1 closer to q
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DDROutput(d[1], d[0], ddr, ClockSignal("rio_phy")),
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DifferentialOutput(ddr, pp, pn),
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]
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ddr = Signal()
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self.specials += [
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DifferentialInput(pins.miso, pins_n.miso, ddr),
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# q1 closer to d
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DDRInput(ddr, self.data[-1][0], self.data[-1][1],
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ClockSignal("rio_phy")),
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]
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