mirror of https://github.com/m-labs/artiq.git
77 lines
2.0 KiB
Python
77 lines
2.0 KiB
Python
# The RTIO channel numbers here are for Phaser on KC705.
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core_addr = "kc705aux.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 5e-9/6}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"ttl_sma": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 0}
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},
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"led": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 1}
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},
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"sysref": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 2}
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},
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"converter_spi": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "NRTSPIMaster",
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},
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"ad9154_spi": {
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"type": "local",
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"module": "artiq.coredevice.ad9154_spi",
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"class": "AD9154",
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"arguments": {"spi_device": "converter_spi", "chip_select": 1}
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},
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"sawg0": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 3, "parallelism": 2}
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},
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"sawg1": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 13, "parallelism": 2}
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},
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"sawg2": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 23, "parallelism": 2}
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},
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"sawg3": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 33, "parallelism": 2}
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}
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}
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