mirror of https://github.com/m-labs/artiq.git
47 lines
1.1 KiB
Rust
47 lines
1.1 KiB
Rust
use core::slice;
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use board::csr::rtm_fpga_cfg;
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use board::clock;
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const ADDR: *const u8 = 0x150000 as *const u8;
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pub fn program_bitstream() -> Result<(), ()> {
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unsafe {
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let length = *(ADDR as *const usize);
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let bitstream = slice::from_raw_parts(ADDR.offset(4) as *const u32, length / 4);
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debug!("resetting");
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rtm_fpga_cfg::divisor_write(15);
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rtm_fpga_cfg::program_write(1);
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clock::spin_us(1000);
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rtm_fpga_cfg::program_write(0);
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clock::spin_us(1000);
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while rtm_fpga_cfg::error_read() != 0 {}
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debug!("programming");
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for word in bitstream {
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rtm_fpga_cfg::data_write(*word);
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rtm_fpga_cfg::start_write(1);
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while rtm_fpga_cfg::busy_read() == 1 {}
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}
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debug!("finishing");
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loop {
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if rtm_fpga_cfg::error_read() != 0 {
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error!("programming error");
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return Err(())
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}
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if rtm_fpga_cfg::done_read() != 0 {
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debug!("done");
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return Ok(())
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}
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}
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}
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}
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