mirror of https://github.com/m-labs/artiq.git
140 lines
3.4 KiB
Python
140 lines
3.4 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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bitseq = [
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# 0 1 2 3 4 5 6
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6, 5, 4, 3, 2, 1, 27,
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# 7 8 9 10 11 12 13
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26, 0, 13, 12, 11, 10, 9,
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# 14 15 16 17 18 19 20
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25, 24, 8, 7, 20, 19, 18,
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# 21 22 23
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17, 23, 22
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]
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assert len(set(bitseq)) == 24
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class Parser(Module, AutoCSR):
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"""Parses 28 bit encoded words and track pixel coordinates."""
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def __init__(self, width=12):
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self.cl = cl = Signal(28)
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self.last_x = CSRStatus(width)
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self.last_y = CSRStatus(width)
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self.pix = pix = Record([
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("x", width),
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("y", width),
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("a", 8),
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("b", 8),
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("c", 8),
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("stb", 1),
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("eop", 1),
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])
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# # #
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last_x = Signal(width)
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last_y = Signal(width)
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lval = Signal()
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fval = Signal()
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dval = Signal()
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last_lval = Signal()
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last_fval = Signal()
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self.comb += [
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Cat(dval, fval, lval).eq(cl[14:17]),
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pix.stb.eq(dval),
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pix.eop.eq(~fval & last_fval),
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Cat(pix.a, pix.b, pix.c).eq(Cat(cl[i] for i in bitseq))
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]
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self.sync.cl += [
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last_lval.eq(lval),
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last_fval.eq(fval),
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pix.x.eq(pix.x + 1),
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If(~lval,
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pix.x.eq(0),
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If(last_lval, last_x.eq(pix.x)),
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If(last_fval & last_lval,
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pix.y.eq(pix.y + 1)
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)
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),
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If(~fval,
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If(last_fval, last_y.eq(pix.y)),
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pix.y.eq(0)
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)
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]
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last_x.attr.add("no_retiming")
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last_y.attr.add("no_retiming")
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self.specials += [
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MultiReg(last_x, self.last_x.status),
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MultiReg(last_y, self.last_y.status)
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]
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class ROI(Module):
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"""ROI Engine. For each frame, accumulates pixels values within a
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rectangular region of interest, and reports the total."""
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def __init__(self, pix, shift=0):
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cnt_len = len(pix.x) + len(pix.y) + 16 - shift
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self.cfg = cfg = Record([
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("x0", len(pix.x)),
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("x1", len(pix.x)),
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("y0", len(pix.y)),
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("y1", len(pix.y)),
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])
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self.out = out = Record([
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("update", 1),
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# register output - can be used as CDC input
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("cnt", cnt_len),
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])
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# # #
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# stage 1 - generate "good" (in-ROI) signals
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y_good = Signal()
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x_good = Signal()
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stb = Signal()
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eop = Signal()
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gray = Signal(16)
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self.sync.cl += [
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If(pix.y == cfg.y0,
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y_good.eq(1)
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),
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If(pix.y == cfg.y1,
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y_good.eq(0)
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),
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If(pix.x == cfg.x0,
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x_good.eq(1)
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),
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If(pix.x == cfg.x1,
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x_good.eq(0)
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),
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gray.eq(Cat(pix.a, pix.b)[shift:]),
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stb.eq(pix.stb),
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eop.eq(pix.eop)
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]
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# stage 2 - accumulate
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cnt = Signal(cnt_len)
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self.sync.cl += [
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If(stb & x_good & y_good,
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cnt.eq(cnt + gray),
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),
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out.update.eq(0),
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If(eop,
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cnt.eq(0),
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out.update.eq(1),
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out.cnt.eq(cnt)
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)
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]
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