mirror of https://github.com/m-labs/artiq.git
83 lines
3.3 KiB
Python
83 lines
3.3 KiB
Python
from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.wrpll.si549 import Si549
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from artiq.gateware.drtio.wrpll.ddmtd import DDMTD
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from artiq.gateware.drtio.wrpll import thls, filters
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self, timer_width=23, counter_width=23, domains=["helper", "rtio", "rtio_rx0"]):
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for domain in domains:
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name = "counter_" + domain
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counter = CSRStatus(counter_width, name=name)
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setattr(self, name, counter)
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self.update_en = CSRStorage()
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timer = Signal(timer_width)
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timer_tick = Signal()
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self.sync += Cat(timer, timer_tick).eq(timer + 1)
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for domain in domains:
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sync_domain = getattr(self.sync, domain)
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divider = Signal(2)
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sync_domain += divider.eq(divider + 1)
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divided = Signal()
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divided.attr.add("no_retiming")
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sync_domain += divided.eq(divider[-1])
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divided_sys = Signal()
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self.specials += MultiReg(divided, divided_sys)
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divided_sys_r = Signal()
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divided_tick = Signal()
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self.sync += divided_sys_r.eq(divided_sys)
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self.comb += divided_tick.eq(divided_sys & ~divided_sys_r)
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counter = Signal(counter_width)
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counter_csr = getattr(self, "counter_" + domain)
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self.sync += [
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If(timer_tick,
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If(self.update_en.storage, counter_csr.status.eq(counter)),
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counter.eq(0),
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).Else(
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If(divided_tick, counter.eq(counter + 1))
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)
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]
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class WRPLL(Module, AutoCSR):
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def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c, ddmtd_inputs, N=15):
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self.helper_reset = CSRStorage(reset=1)
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self.clock_domains.cd_helper = ClockDomain()
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self.helper_reset.storage.attr.add("no_retiming")
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self.specials += [
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Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n,
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o_O=self.cd_helper.clk),
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AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
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]
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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# for diagnostics and PLL initialization
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self.submodules.frequency_counter = FrequencyCounter()
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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helper_cd = ClockDomainsRenamer("helper")
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self.submodules.filter_helper = helper_cd(thls.make(filters.helper, data_width=48))
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self.submodules.filter_main = helper_cd(thls.make(filters.main, data_width=48))
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self.comb += [
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self.helper_dcxo.adpll_stb.eq(self.filter_helper.output_stb),
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self.helper_dcxo.adpll.eq(self.filter_helper.output),
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self.main_dcxo.adpll_stb.eq(self.filter_main.output_stb),
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self.main_dcxo.adpll.eq(self.filter_main.output)
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]
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