mirror of https://github.com/m-labs/artiq.git
306 lines
9.3 KiB
Python
306 lines
9.3 KiB
Python
import numpy
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from artiq.language.core import *
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from artiq.language.types import *
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.coredevice import spi2 as spi
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from artiq.language.units import us
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@portable
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def shuttler_volt_to_mu(volt):
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# TODO: Check arg, raise exception if exceeds shuttler limit
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return int(round((1 << 14) * (volt / 20.0))) & 0x3fff
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class Config:
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kernel_invariants = {
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"core", "channel", "target_base", "target_read",
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"target_gain", "target_offset", "target_clr"
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}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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self.target_base = channel << 8
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self.target_read = 1 << 6
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self.target_gain = 0 * (1 << 4)
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self.target_offset = 1 * (1 << 4)
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self.target_clr = 1 * (1 << 5)
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@kernel
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def set_clr(self, clr):
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rtio_output(self.target_base | self.target_clr, clr)
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@kernel
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def set_gain(self, channel, gain):
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rtio_output(self.target_base | self.target_gain | channel, gain)
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@kernel
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def get_gain(self, channel):
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rtio_output(self.target_base | self.target_gain |
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self.target_read | channel, 0)
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return rtio_input_data(self.channel)
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@kernel
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def set_offset(self, channel, offset):
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rtio_output(self.target_base | self.target_offset | channel, offset)
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@kernel
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def get_offset(self, channel):
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rtio_output(self.target_base | self.target_offset |
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self.target_read | channel, 0)
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return rtio_input_data(self.channel)
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class Volt:
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kernel_invariants = {"core", "channel", "target_o"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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self.target_o = channel << 8
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@kernel
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def set_waveform(self, a0: TInt32, a1: TInt32, a2: TInt64, a3: TInt64):
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pdq_words = [
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a0,
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a1,
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a1 >> 16,
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a2 & 0xFFFF,
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(a2 >> 16) & 0xFFFF,
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(a2 >> 32) & 0xFFFF,
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a3 & 0xFFFF,
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(a3 >> 16) & 0xFFFF,
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(a3 >> 32) & 0xFFFF,
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]
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for i in range(len(pdq_words)):
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rtio_output(self.target_o | i, pdq_words[i])
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delay_mu(int64(self.core.ref_multiplier))
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class Dds:
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kernel_invariants = {"core", "channel", "target_o"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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self.target_o = channel << 8
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@kernel
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def set_waveform(self, b0: TInt32, b1: TInt32, b2: TInt64, b3: TInt64,
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c0: TInt32, c1: TInt32, c2: TInt32):
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pdq_words = [
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b0,
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b1,
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b1 >> 16,
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b2 & 0xFFFF,
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(b2 >> 16) & 0xFFFF,
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(b2 >> 32) & 0xFFFF,
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b3 & 0xFFFF,
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(b3 >> 16) & 0xFFFF,
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(b3 >> 32) & 0xFFFF,
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c0,
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c1,
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c1 >> 16,
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c2,
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c2 >> 16,
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]
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for i in range(len(pdq_words)):
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rtio_output(self.target_o | i, pdq_words[i])
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delay_mu(int64(self.core.ref_multiplier))
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class Trigger:
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kernel_invariants = {"core", "channel", "target_o"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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self.target_o = channel << 8
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@kernel
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def trigger(self, trig_out):
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rtio_output(self.target_o, trig_out)
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RELAY_SPI_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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ADC_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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1*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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# SPI clock write and read dividers
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# CS should assert at least 9.5 ns after clk pulse
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SPIT_RELAY_WR = 4
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# 25 ns high/low pulse hold (limiting for write)
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SPIT_ADC_WR = 4
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SPIT_ADC_RD = 16
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# SPI CS line
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CS_RELAY = 1 << 0
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CS_LED = 1 << 1
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CS_ADC = 1 << 0
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# Referenced AD4115 registers
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_AD4115_REG_STATUS = 0x00
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_AD4115_REG_ADCMODE = 0x01
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_AD4115_REG_DATA = 0x04
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_AD4115_REG_ID = 0x07
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_AD4115_REG_CH0 = 0x10
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_AD4115_REG_SETUPCON0 = 0x20
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class Relay:
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kernel_invariant = {"core", "bus"}
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def __init__(self, dmgr, spi_device, core_device="core"):
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self.core = dmgr.get(core_device)
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self.bus = dmgr.get(spi_device)
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@kernel
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def init(self):
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self.bus.set_config_mu(
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RELAY_SPI_CONFIG, 16, SPIT_RELAY_WR, CS_RELAY | CS_LED)
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@kernel
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def set_led(self, leds: TInt32):
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self.bus.write(leds << 16)
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class ADC:
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kernel_invariant = {"core", "bus"}
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def __init__(self, dmgr, spi_device, core_device="core"):
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self.core = dmgr.get(core_device)
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self.bus = dmgr.get(spi_device)
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@kernel
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def read_id(self) -> TInt32:
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return self.read16(_AD4115_REG_ID)
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@kernel
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def reset(self):
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# Hold DIN high for 64 cycles
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# However, asserting CS right after the 64 cycles seems to interrupt
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# the start-up sequence.
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self.bus.set_config_mu(ADC_SPI_CONFIG, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(0xffffffff)
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self.bus.write(0xffffffff)
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(0xffffffff)
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@kernel
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def read8(self, addr: TInt32) -> TInt32:
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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16, SPIT_ADC_RD, CS_ADC)
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self.bus.write((addr | 0x40) << 24)
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return self.bus.read() & 0xff
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@kernel
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def read16(self, addr: TInt32) -> TInt32:
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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24, SPIT_ADC_RD, CS_ADC)
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self.bus.write((addr | 0x40) << 24)
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return self.bus.read() & 0xffff
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@kernel
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def read24(self, addr: TInt32) -> TInt32:
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, SPIT_ADC_RD, CS_ADC)
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self.bus.write((addr | 0x40) << 24)
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return self.bus.read() & 0xffffff
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@kernel
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def write8(self, addr: TInt32, data: TInt32):
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 16, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xff) << 16)
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@kernel
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def write16(self, addr: TInt32, data: TInt32):
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 24, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xffff) << 8)
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@kernel
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def write24(self, addr: TInt32, data: TInt32):
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xffffff))
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@kernel
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def read_ch(self, channel: TInt32) -> TFloat:
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# Always configure Profile 0 for single conversion
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self.write16(_AD4115_REG_CH0, 0x8000 | ((channel * 2 + 1) << 4))
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self.write16(_AD4115_REG_SETUPCON0, 0x1300)
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self.write16(_AD4115_REG_ADCMODE, 0x8010)
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delay(100*us)
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adc_code = self.read24(_AD4115_REG_DATA)
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return ((adc_code / (1 << 23)) - 1) * 2.5 / 0.1
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@kernel
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def standby(self):
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# Selecting internal XO (0b00) also disables clock during standby
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self.write16(_AD4115_REG_ADCMODE, 0x8020)
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@kernel
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def power_down(self):
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self.write16(_AD4115_REG_ADCMODE, 0x8030)
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@kernel
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def exit_power_down(self):
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self.reset()
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# Although the datasheet claims 500 us reset wait time, only waiting
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# for ~500 us can result in DOUT pin stuck in high
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delay(2500*us)
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@kernel
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def calibrate(self, volts, trigger, config, samples=[-5.0, 0.0, 5.0]):
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assert len(volts) == 16
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assert len(samples) > 1
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measurements = [0.0] * len(samples)
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for ch in range(16):
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# Find the average slope rate and offset
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for i in range(len(samples)):
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self.core.break_realtime()
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volts[ch].set_waveform(
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shuttler_volt_to_mu(samples[i]), 0, 0, 0)
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trigger.trigger(1 << ch)
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measurements[i] = self.read_ch(ch)
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# Find the average output slope
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slope_sum = 0.0
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for i in range(len(samples) - 1):
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slope_sum += (measurements[i+1] - measurements[i])/(samples[i+1] - samples[i])
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slope_avg = slope_sum / (len(samples) - 1)
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gain_code = int32(1 / slope_avg * (2 ** 16)) & 0xffff
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# Scale the measurements by 1/slope, find average offset
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offset_sum = 0.0
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for i in range(len(samples)):
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offset_sum += (measurements[i] / slope_avg) - samples[i]
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offset_avg = offset_sum / len(samples)
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offset_code = shuttler_volt_to_mu(-offset_avg)
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self.core.break_realtime()
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config.set_gain(ch, gain_code)
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delay_mu(int64(self.core.ref_multiplier))
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config.set_offset(ch, offset_code)
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