mirror of https://github.com/m-labs/artiq.git
394 lines
13 KiB
Python
394 lines
13 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect.csr import *
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from artiq.gateware.serwb.kusphy import KUSSerdes
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from artiq.gateware.serwb.s7phy import S7Serdes
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# Master <--> Slave synchronization:
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# 1) Master sends idle pattern (zeroes) to reset Slave.
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# 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle pattern.
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# 3) Slave sends K28.5 commas to allow Master to calibrate, Master sends K28.5 commas.
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# 4) Master stops sending K28.5 commas.
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# 5) Slave stops sending K28.5 commas.
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# 6) Link is ready.
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class _SerdesMasterInit(Module):
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def __init__(self, serdes, taps, timeout=1024):
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self.reset = Signal()
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self.ready = Signal()
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self.error = Signal()
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# # #
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self.delay = delay = Signal(max=taps)
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self.delay_min = delay_min = Signal(max=taps)
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self.delay_min_found = delay_min_found = Signal()
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self.delay_max = delay_max = Signal(max=taps)
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self.delay_max_found = delay_max_found = Signal()
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self.bitslip = bitslip = Signal(max=40)
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timer = WaitTimer(timeout)
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self.submodules += timer
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
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self.comb += self.fsm.reset.eq(self.reset)
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self.comb += serdes.rx_delay_inc.eq(1)
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fsm.act("IDLE",
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NextValue(delay, 0),
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NextValue(delay_min, 0),
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NextValue(delay_min_found, 0),
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NextValue(delay_max, 0),
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NextValue(delay_max_found, 0),
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serdes.rx_delay_rst.eq(1),
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NextValue(bitslip, 0),
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NextState("RESET_SLAVE"),
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serdes.tx_idle.eq(1)
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)
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fsm.act("RESET_SLAVE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("SEND_PATTERN")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("SEND_PATTERN",
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If(~serdes.rx_idle,
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NextState("WAIT_STABLE")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("WAIT_STABLE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CHECK_PATTERN")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(~delay_min_found,
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextValue(delay_min, delay),
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NextValue(delay_min_found, 1)
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)
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).Else(
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NextState("INC_DELAY_BITSLIP")
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),
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).Else(
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If(~serdes.rx_comma,
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NextValue(delay_max, delay),
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NextValue(delay_max_found, 1),
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NextState("CHECK_SAMPLING_WINDOW")
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).Else(
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NextState("INC_DELAY_BITSLIP")
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)
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),
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serdes.tx_comma.eq(1)
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)
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self.comb += serdes.rx_bitslip_value.eq(bitslip)
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fsm.act("INC_DELAY_BITSLIP",
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NextState("WAIT_STABLE"),
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If(delay == (taps - 1),
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If(bitslip == (40 - 1),
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NextState("ERROR")
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).Else(
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NextValue(delay_min_found, 0),
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NextValue(bitslip, bitslip + 1)
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),
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1)
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_ce.eq(1)
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CHECK_SAMPLING_WINDOW",
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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NextValue(delay_min_found, 0),
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NextValue(delay_max_found, 0),
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NextState("WAIT_STABLE")
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).Else(
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CONFIGURE_SAMPLING_WINDOW",
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If(delay == (delay_min + (delay_max - delay_min)[1:]),
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NextState("READY")
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1),
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NextState("WAIT_SAMPLING_WINDOW")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("WAIT_SAMPLING_WINDOW",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("READY",
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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self.error.eq(1)
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)
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class _SerdesSlaveInit(Module, AutoCSR):
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def __init__(self, serdes, taps, timeout=1024):
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self.reset = Signal()
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self.ready = Signal()
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self.error = Signal()
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# # #
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self.delay = delay = Signal(max=taps)
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self.delay_min = delay_min = Signal(max=taps)
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self.delay_min_found = delay_min_found = Signal()
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self.delay_max = delay_max = Signal(max=taps)
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self.delay_max_found = delay_max_found = Signal()
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self.bitslip = bitslip = Signal(max=40)
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timer = WaitTimer(timeout)
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self.submodules += timer
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self.comb += self.reset.eq(serdes.rx_idle)
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self.comb += serdes.rx_delay_inc.eq(1)
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
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fsm.act("IDLE",
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NextValue(delay, 0),
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NextValue(delay_min, 0),
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NextValue(delay_min_found, 0),
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NextValue(delay_max, 0),
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NextValue(delay_max_found, 0),
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serdes.rx_delay_rst.eq(1),
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NextValue(bitslip, 0),
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NextState("WAIT_STABLE"),
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serdes.tx_idle.eq(1)
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)
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fsm.act("WAIT_STABLE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CHECK_PATTERN")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(~delay_min_found,
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextValue(delay_min, delay),
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NextValue(delay_min_found, 1)
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)
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).Else(
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NextState("INC_DELAY_BITSLIP")
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),
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).Else(
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If(~serdes.rx_comma,
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NextValue(delay_max, delay),
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NextValue(delay_max_found, 1),
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NextState("CHECK_SAMPLING_WINDOW")
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).Else(
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NextState("INC_DELAY_BITSLIP")
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)
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),
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serdes.tx_idle.eq(1)
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)
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self.comb += serdes.rx_bitslip_value.eq(bitslip)
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fsm.act("INC_DELAY_BITSLIP",
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NextState("WAIT_STABLE"),
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If(delay == (taps - 1),
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If(bitslip == (40 - 1),
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NextState("ERROR")
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).Else(
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NextValue(delay_min_found, 0),
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NextValue(bitslip, bitslip + 1)
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),
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1)
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_ce.eq(1)
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CHECK_SAMPLING_WINDOW",
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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NextValue(delay_min_found, 0),
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NextValue(delay_max_found, 0),
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NextState("WAIT_STABLE")
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).Else(
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CONFIGURE_SAMPLING_WINDOW",
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If(delay == (delay_min + (delay_max - delay_min)[1:]),
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NextState("SEND_PATTERN")
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1),
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NextState("WAIT_SAMPLING_WINDOW")
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)
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)
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fsm.act("WAIT_SAMPLING_WINDOW",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CONFIGURE_SAMPLING_WINDOW")
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)
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)
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fsm.act("SEND_PATTERN",
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timer.wait.eq(1),
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If(timer.done,
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If(~serdes.rx_comma,
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NextState("READY")
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)
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("READY",
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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self.error.eq(1)
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)
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class _SerdesControl(Module, AutoCSR):
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def __init__(self, init, mode="master"):
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if mode == "master":
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self.reset = CSR()
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self.ready = CSRStatus()
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self.error = CSRStatus()
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self.delay = CSRStatus(9)
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self.delay_min_found = CSRStatus()
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self.delay_min = CSRStatus(9)
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self.delay_max_found = CSRStatus()
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self.delay_max = CSRStatus(9)
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self.bitslip = CSRStatus(6)
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# # #
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if mode == "master":
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self.comb += init.reset.eq(self.reset.re)
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self.comb += [
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self.ready.status.eq(init.ready),
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self.error.status.eq(init.error),
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self.delay.status.eq(init.delay),
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self.delay_min_found.status.eq(init.delay_min_found),
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self.delay_min.status.eq(init.delay_min),
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self.delay_max_found.status.eq(init.delay_max_found),
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self.delay_max.status.eq(init.delay_max),
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self.bitslip.status.eq(init.bitslip)
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]
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class SERWBPLL(Module):
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def __init__(self, refclk_freq, linerate, vco_div=1):
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assert refclk_freq == 125e6
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assert linerate == 1.25e9
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self.lock = Signal()
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self.refclk = Signal()
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self.serwb_serdes_clk = Signal()
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self.serwb_serdes_20x_clk = Signal()
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self.serwb_serdes_5x_clk = Signal()
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# # #
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#----------------------------
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# refclk: 125MHz
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# vco: 1250MHz
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#----------------------------
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# serwb_serdes: 31.25MHz
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# serwb_serdes_20x: 625MHz
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# serwb_serdes_5x: 156.25MHz
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#----------------------------
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self.linerate = linerate
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pll_locked = Signal()
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pll_fb = Signal()
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pll_serwb_serdes_clk = Signal()
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pll_serwb_serdes_20x_clk = Signal()
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pll_serwb_serdes_5x_clk = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1.25GHz / vco_div
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0,
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p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=vco_div,
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i_CLKIN1=self.refclk, i_CLKFBIN=pll_fb,
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o_CLKFBOUT=pll_fb,
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# 31.25MHz: serwb_serdes
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p_CLKOUT0_DIVIDE=40//vco_div, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_serwb_serdes_clk,
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# 625MHz: serwb_serdes_20x
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p_CLKOUT1_DIVIDE=2//vco_div, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_serwb_serdes_20x_clk,
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# 156.25MHz: serwb_serdes_5x
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p_CLKOUT2_DIVIDE=8//vco_div, p_CLKOUT2_PHASE=0.0,
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o_CLKOUT2=pll_serwb_serdes_5x_clk
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),
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Instance("BUFG",
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i_I=pll_serwb_serdes_clk,
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o_O=self.serwb_serdes_clk),
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Instance("BUFG",
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i_I=pll_serwb_serdes_20x_clk,
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o_O=self.serwb_serdes_20x_clk),
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Instance("BUFG",
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i_I=pll_serwb_serdes_5x_clk,
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o_O=self.serwb_serdes_5x_clk)
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]
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self.specials += MultiReg(pll_locked, self.lock)
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class SERWBPHY(Module, AutoCSR):
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def __init__(self, device, pll, pads, mode="master"):
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assert mode in ["master", "slave"]
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if device[:4] == "xcku":
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taps = 512
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self.submodules.serdes = KUSSerdes(pll, pads, mode)
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elif device[:4] == "xc7a":
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taps = 32
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self.submodules.serdes = S7Serdes(pll, pads, mode)
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else:
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raise NotImplementedError
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if mode == "master":
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self.submodules.init = _SerdesMasterInit(self.serdes, taps)
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else:
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self.submodules.init = _SerdesSlaveInit(self.serdes, taps)
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self.submodules.control = _SerdesControl(self.init, mode)
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