mirror of https://github.com/m-labs/artiq.git
106 lines
3.7 KiB
Python
106 lines
3.7 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from targets.kc705 import BaseSoC
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from artiq.gateware import amp, rtio, ad9858, nist_qc1
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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rtio_external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_S=self._clock_sel.storage,
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o_O=self.cd_rtio.clk)
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class _Peripherals(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type, **kwargs)
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platform.add_extension(nist_qc1.fmc_adapter_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1)))
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fud = Signal()
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(16)]
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rtio_outs.append(platform.request("user_led", 2))
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rtio_outs.append(fud)
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self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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rtio_ins + rtio_outs,
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output_only_pads=set(rtio_outs))
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self.submodules.rtio = rtio.RTIO(self.rtiophy,
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clk_freq=125000000,
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ififo_depth=512)
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.comb += dds_pads.fud_n.eq(~fud)
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class UP(_Peripherals):
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def __init__(self, *args, **kwargs):
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_Peripherals.__init__(self, *args, **kwargs)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_Peripherals.csr_map)
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def __init__(self, platform, *args, **kwargs):
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_Peripherals.__init__(self, platform, *args, **kwargs)
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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default_subtarget = UP
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