mirror of https://github.com/m-labs/artiq.git
212 lines
7.1 KiB
Python
212 lines
7.1 KiB
Python
from artiq.language.core import kernel, delay_mu, delay, portable
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from artiq.language.units import us, ns, ms
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from artiq.coredevice.urukul import urukul_sta_pll_lock
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from numpy import int32, int64
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_AD9910_REG_CFR1 = 0x00
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_AD9910_REG_CFR2 = 0x01
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_AD9910_REG_CFR3 = 0x02
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_AD9910_REG_AUX_DAC = 0x03
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_AD9910_REG_IO_UPD = 0x04
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_AD9910_REG_FTW = 0x07
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_AD9910_REG_POW = 0x08
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_AD9910_REG_ASF = 0x09
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_AD9910_REG_MSYNC = 0x0A
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_AD9910_REG_DRAMPL = 0x0B
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_AD9910_REG_DRAMPS = 0x0C
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_AD9910_REG_DRAMPR = 0x0D
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_AD9910_REG_PR0 = 0x0E
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_AD9910_REG_PR1 = 0x0F
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_AD9910_REG_PR2 = 0x10
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_AD9910_REG_PR3 = 0x11
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_AD9910_REG_PR4 = 0x12
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_AD9910_REG_PR5 = 0x13
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_AD9910_REG_PR6 = 0x14
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_AD9910_REG_PR7 = 0x15
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_AD9910_REG_RAM = 0x16
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class AD9910:
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"""
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AD9910 DDS channel on Urukul.
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This class supports a single DDS channel and exposes the DDS,
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the digital step attenuator, and the RF switch.
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:param chip_select: Chip select configuration. On Urukul this is an
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encoded chip select and not "one-hot".
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:param cpld_device: Name of the Urukul CPLD this device is on.
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:param sw_device: Name of the RF switch device. The RF switch is a
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TTLOut channel available as the :attr:`sw` attribute of this instance.
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:param pll_n: DDS PLL multiplier. The DDS sample clock is
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f_ref/4*pll_n where f_ref is the reference frequency (set in the parent
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Urukul CPLD instance).
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:param pll_cp: DDS PLL charge pump setting.
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:param pll_vco: DDS PLL VCO range selection.
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus", "sw",
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"ftw_per_hz", "sysclk", "pll_n", "pll_cp", "pll_vco"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=40, pll_cp=7, pll_vco=5):
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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assert 4 <= chip_select <= 7
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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assert 12 <= pll_n <= 127
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self.pll_n = pll_n
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assert self.cpld.refclk < 60e6
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self.sysclk = self.cpld.refclk*pll_n/4 # Urukul clock fanout divider
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assert self.sysclk < 1e9
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self.ftw_per_hz = 1./self.sysclk*(int64(1) << 32)
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assert 0 <= pll_vco <= 5
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vco_min, vco_max = [(370, 510), (420, 590), (500, 700),
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(600, 880), (700, 950), (820, 1150)][pll_vco]
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assert vco_min <= self.sysclk/1e6 <= vco_max
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self.pll_vco = pll_vco
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assert 0 <= pll_cp <= 7
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self.pll_cp = pll_cp
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@kernel
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def write32(self, addr, data):
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"""Write to 32 bit register.
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:param addr: Register address
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:param data: Data to be written
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"""
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self.bus.set_xfer(self.chip_select, 8, 0)
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self.bus.write(addr << 24)
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delay_mu(-self.bus.xfer_period_mu + 8)
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self.bus.set_xfer(self.chip_select, 32, 0)
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self.bus.write(data)
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delay_mu(self.bus.xfer_period_mu - self.bus.write_period_mu)
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@kernel
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def write64(self, addr, data_high, data_low):
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"""Write to 64 bit register.
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:param addr: Register address
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:param data_high: High (MSB) 32 bits of the data
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:param data_low: Low (LSB) 32 data bits
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"""
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self.bus.set_xfer(self.chip_select, 8, 0)
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self.bus.write(addr << 24)
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t = self.bus.xfer_period_mu
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delay_mu(-t + 8)
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self.bus.set_xfer(self.chip_select, 32, 0)
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self.bus.write(data_high)
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self.bus.write(data_low)
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delay_mu(t - 2*self.bus.write_period_mu)
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@kernel
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def read32(self, addr):
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"""Read from 32 bit register.
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:param addr: Register address
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"""
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self.bus.set_xfer(self.chip_select, 8, 0)
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self.bus.write((addr | 0x80) << 24)
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delay_mu(-self.bus.xfer_period_mu + 8)
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self.bus.set_xfer(self.chip_select, 0, 32)
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self.bus.write(0)
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delay_mu(2*self.bus.xfer_period_mu)
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data = self.bus.read_sync()
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return data
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@kernel
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def init(self):
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"""Initialize and configure the DDS."""
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# Set SPI mode
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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delay(100*us)
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self.cpld.io_update.pulse(100*ns)
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# Use the AUX DAC setting to identify and confirm presence
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aux_dac = self.read32(_AD9910_REG_AUX_DAC)
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if aux_dac & 0xff != 0x7f:
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raise ValueError("Urukul AD9910 AUX_DAC mismatch")
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delay(100*us)
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# Configure PLL settings and bring up PLL
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self.write32(_AD9910_REG_CFR2, 0x01400020)
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cfr3 = (0x0807c100 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_n << 1))
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self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
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delay(100*us)
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self.cpld.io_update.pulse(100*ns)
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self.write32(_AD9910_REG_CFR3, cfr3)
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delay(100*us)
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self.cpld.io_update.pulse(100*ns)
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# Wait for PLL lock, up to 100 ms
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for i in range(100):
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lock = urukul_sta_pll_lock(self.cpld.sta_read())
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delay(1*ms)
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if lock & (1 << self.chip_select - 4) != 0:
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return
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raise ValueError("PLL failed to lock")
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@kernel
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def set_mu(self, ftw, pow=0, asf=0x3fff):
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"""Set profile 0 data in machine units.
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After the SPI transfer, the shared IO update pin is pulsed to
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activate the data.
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:param ftw: Frequency tuning word: 32 bit unsigned.
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:param pow: Phase tuning word: 16 bit unsigned.
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:param asf: Amplitude scale factor: 14 bit unsigned.
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"""
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self.write64(_AD9910_REG_PR0, (asf << 16) | pow, ftw)
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self.cpld.io_update.pulse(10*ns)
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return int32(round(self.ftw_per_hz*frequency))
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@portable(flags={"fast-math"})
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def turns_to_pow(self, turns):
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"""Returns the phase offset word corresponding to the given phase
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in turns."""
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return int32(round(turns*0x10000))
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@portable(flags={"fast-math"})
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def amplitude_to_asf(self, amplitude):
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"""Returns amplitude scale factor corresponding to given amplitude."""
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return int32(round(amplitude*0x3ffe))
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@kernel
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def set(self, frequency, phase=0.0, amplitude=1.0):
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"""Set profile 0 data in SI units.
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.. seealso:: :meth:`set_mu`
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:param ftw: Frequency in Hz
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:param pow: Phase tuning word in turns
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:param asf: Amplitude in units of full scale
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"""
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self.set_mu(self.frequency_to_ftw(frequency),
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self.turns_to_pow(phase),
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self.amplitude_to_asf(amplitude))
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@kernel
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def set_att_mu(self, att):
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"""Set digital step attenuator in machine units.
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:param att: Attenuation setting, 8 bit digital.
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"""
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self.cpld.set_att_mu(self.chip_select - 4, att)
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@kernel
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def set_att(self, att):
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"""Set digital step attenuator in SI units.
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:param att: Attenuation in dB.
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"""
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self.cpld.set_att(self.chip_select - 4, att)
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