mirror of https://github.com/m-labs/artiq.git
356 lines
11 KiB
Python
356 lines
11 KiB
Python
from artiq.experiment import *
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from artiq.test.hardware_testbench import ExperimentCase
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from artiq.coredevice.ad9910 import (
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_AD9910_REG_FTW, _AD9910_REG_PROFILE0, RAM_MODE_RAMPUP,
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RAM_DEST_FTW)
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from artiq.coredevice.urukul import (
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urukul_sta_smp_err, CFG_CLK_SEL0, CFG_CLK_SEL1)
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class AD9910Exp(EnvExperiment):
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def build(self, runner):
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self.setattr_device("core")
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self.dev = self.get_device("urukul_ad9910")
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self.runner = runner
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def run(self):
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getattr(self, self.runner)()
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@kernel
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def instantiate(self):
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pass
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@kernel
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def init(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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@kernel
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def init_fail(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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cfg = self.dev.cpld.cfg_reg
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cfg &= ~(1 << CFG_CLK_SEL1)
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cfg |= 1 << CFG_CLK_SEL0
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self.dev.cpld.cfg_write(cfg)
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# clk_sel=1, external SMA, should fail PLL lock
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self.dev.init()
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@kernel
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def set_get(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.set_att(20*dB)
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f = 81.2345*MHz
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self.dev.set(frequency=f, phase=.33, amplitude=.89)
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self.set_dataset("ftw_set", self.dev.frequency_to_ftw(f))
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self.set_dataset("ftw_get", self.dev.read32(_AD9910_REG_FTW))
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@kernel
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def read_write64(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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lo = 0x12345678
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hi = 0x09abcdef
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self.dev.write64(_AD9910_REG_PROFILE0, hi, lo)
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self.dev.cpld.io_update.pulse_mu(8)
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read = self.dev.read64(_AD9910_REG_PROFILE0)
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self.set_dataset("write", (int64(hi) << 32) | lo)
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self.set_dataset("read", read)
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@kernel
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def set_speed(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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f = 81.2345*MHz
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n = 10
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t0 = self.core.get_rtio_counter_mu()
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for i in range(n):
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self.dev.set(frequency=f, phase=.33, amplitude=.89)
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self.set_dataset("dt", self.core.mu_to_seconds(
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self.core.get_rtio_counter_mu() - t0)/n)
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@kernel
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def set_speed_mu(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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n = 10
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t0 = self.core.get_rtio_counter_mu()
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for i in range(n):
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self.dev.set_mu(0x12345678, 0x1234, 0x4321)
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self.set_dataset("dt", self.core.mu_to_seconds(
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self.core.get_rtio_counter_mu() - t0)/n)
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@kernel
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def sync_window(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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err = [0] * 32
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for i in range(6):
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self.sync_scan(err, win=i)
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print(err)
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self.core.break_realtime()
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dly, win = self.dev.tune_sync_delay()
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self.sync_scan(err, win=win)
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# FIXME: win + 1 # tighten window by 2*75ps
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# after https://github.com/sinara-hw/Urukul/issues/16
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self.set_dataset("dly", dly)
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self.set_dataset("win", win)
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self.set_dataset("err", err)
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@kernel
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def sync_scan(self, err, win):
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for in_delay in range(len(err)):
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self.dev.set_sync(in_delay=in_delay, window=win)
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self.dev.clear_smp_err()
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# delay(10*us) # integrate SMP_ERR statistics
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e = urukul_sta_smp_err(self.dev.cpld.sta_read())
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err[in_delay] = (e >> (self.dev.chip_select - 4)) & 1
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delay(50*us) # slack
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@kernel
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def io_update_delay(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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bins1 = [0]*4
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bins2 = [0]*4
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self.scan_io_delay(bins1, bins2)
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self.set_dataset("bins1", bins1)
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self.set_dataset("bins2", bins2)
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self.set_dataset("dly", self.dev.tune_io_update_delay())
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@kernel
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def scan_io_delay(self, bins1, bins2):
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delay(100*us)
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n = 100
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for i in range(n):
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for j in range(len(bins1)):
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bins1[j] += self.dev.measure_io_update_alignment(j, j + 1)
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bins2[j] += self.dev.measure_io_update_alignment(j, j + 2)
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delay(10*ms)
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@kernel
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def sw_readback(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.cfg_sw(0)
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self.dev.sw.on()
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sw_on = (self.dev.cpld.sta_read() >> (self.dev.chip_select - 4)) & 1
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delay(10*us)
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self.dev.sw.off()
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sw_off = (self.dev.cpld.sta_read() >> (self.dev.chip_select - 4)) & 1
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self.set_dataset("sw", (sw_on, sw_off))
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@kernel
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def profile_readback(self):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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for i in range(8):
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self.dev.set_mu(ftw=i, profile=i)
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ftw = [0] * 8
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for i in range(8):
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self.dev.cpld.set_profile(i)
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# If PROFILE is not alligned to SYNC_CLK a multi-bit change
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# doesn't transfer cleanly. Use IO_UPDATE to load the profile
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# again.
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self.dev.cpld.io_update.pulse_mu(8)
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ftw[i] = self.dev.read32(_AD9910_REG_FTW)
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delay(100*us)
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self.set_dataset("ftw", ftw)
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@kernel
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def ram_write(self):
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n = 1 << 10
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write = [0]*n
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for i in range(n):
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write[i] = i | (i << 16)
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read = [0]*n
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.set_cfr1(ram_enable=0)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.set_profile_ram(
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start=0, end=0 + n - 1, step=1,
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profile=0, mode=RAM_MODE_RAMPUP)
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self.dev.cpld.set_profile(0)
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self.dev.cpld.io_update.pulse_mu(8)
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delay(1*ms)
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self.dev.write_ram(write)
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delay(1*ms)
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self.dev.read_ram(read)
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self.set_dataset("w", write)
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self.set_dataset("r", read)
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@kernel
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def ram_read_overlapping(self):
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write = [0]*989
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for i in range(len(write)):
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write[i] = i
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read = [0]*100
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offset = 367
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.set_cfr1(ram_enable=0)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.set_profile_ram(
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start=0, end=0 + len(write) - 1, step=1,
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profile=0, mode=RAM_MODE_RAMPUP)
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self.dev.set_profile_ram(
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start=offset, end=offset + len(read) - 1, step=1,
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profile=1, mode=RAM_MODE_RAMPUP)
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self.dev.cpld.set_profile(0)
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self.dev.cpld.io_update.pulse_mu(8)
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delay(1*ms)
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self.dev.write_ram(write)
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delay(1*ms)
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self.dev.cpld.set_profile(1)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.read_ram(read)
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# RAM profile addresses are apparently aligned
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# to the last address of the RAM
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start = len(write) - offset - len(read)
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end = len(write) - offset
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self.set_dataset("w", write[start:end])
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self.set_dataset("r", read)
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@kernel
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def ram_exec(self):
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ftw0 = [0x12345678]*10
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ftw1 = [0x55aaaa55]*10
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.set_cfr1(ram_enable=0)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.set_profile_ram(
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start=100, end=100 + len(ftw0) - 1, step=1,
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profile=3, mode=RAM_MODE_RAMPUP)
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self.dev.set_profile_ram(
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start=200, end=200 + len(ftw1) - 1, step=1,
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profile=4, mode=RAM_MODE_RAMPUP)
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self.dev.cpld.set_profile(3)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.write_ram(ftw0)
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self.dev.cpld.set_profile(4)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.write_ram(ftw1)
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self.dev.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_FTW)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.cpld.set_profile(3)
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self.dev.cpld.io_update.pulse_mu(8)
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ftw0r = self.dev.read32(_AD9910_REG_FTW)
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delay(100*us)
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self.dev.cpld.set_profile(4)
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self.dev.cpld.io_update.pulse_mu(8)
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ftw1r = self.dev.read32(_AD9910_REG_FTW)
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self.set_dataset("ftw", [ftw0[0], ftw0r, ftw1[0], ftw1r])
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class AD9910Test(ExperimentCase):
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def test_instantiate(self):
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self.execute(AD9910Exp, "instantiate")
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def test_init(self):
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self.execute(AD9910Exp, "init")
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def test_init_fail(self):
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with self.assertRaises(ValueError):
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self.execute(AD9910Exp, "init_fail")
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def test_set_get(self):
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self.execute(AD9910Exp, "set_get")
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ftw_get = self.dataset_mgr.get("ftw_get")
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ftw_set = self.dataset_mgr.get("ftw_set")
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self.assertEqual(ftw_get, ftw_set)
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def test_read_write64(self):
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self.execute(AD9910Exp, "read_write64")
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write = self.dataset_mgr.get("write")
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read = self.dataset_mgr.get("read")
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self.assertEqual(hex(write), hex(read))
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def test_set_speed(self):
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self.execute(AD9910Exp, "set_speed")
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dt = self.dataset_mgr.get("dt")
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print(dt)
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self.assertLess(dt, 70*us)
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def test_set_speed_mu(self):
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self.execute(AD9910Exp, "set_speed_mu")
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dt = self.dataset_mgr.get("dt")
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print(dt)
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self.assertLess(dt, 11*us)
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def test_sync_window(self):
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self.execute(AD9910Exp, "sync_window")
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err = self.dataset_mgr.get("err")
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dly = self.dataset_mgr.get("dly")
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win = self.dataset_mgr.get("win")
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print(dly, win, err)
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# make sure one tap margin on either side of optimal delay
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for i in -1, 0, 1:
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self.assertEqual(err[i + dly], 0)
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def test_io_update_delay(self):
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self.execute(AD9910Exp, "io_update_delay")
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dly = self.dataset_mgr.get("dly")
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bins1 = self.dataset_mgr.get("bins1")
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bins2 = self.dataset_mgr.get("bins2")
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print(dly, bins1, bins2)
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n = max(bins2)
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# no edge at optimal delay
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self.assertEqual(bins2[(dly + 1) & 3], 0)
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# many edges near expected position
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self.assertGreater(bins2[(dly + 3) & 3], n*.9)
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def test_sw_readback(self):
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self.execute(AD9910Exp, "sw_readback")
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self.assertEqual(self.dataset_mgr.get("sw"), (1, 0))
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def test_profile_readback(self):
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self.execute(AD9910Exp, "profile_readback")
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self.assertEqual(self.dataset_mgr.get("ftw"), list(range(8)))
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def test_ram_write(self):
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self.execute(AD9910Exp, "ram_write")
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read = self.dataset_mgr.get("r")
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write = self.dataset_mgr.get("w")
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self.assertEqual(len(read), len(write))
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self.assertEqual(read, write)
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def test_ram_read_overlapping(self):
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self.execute(AD9910Exp, "ram_read_overlapping")
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read = self.dataset_mgr.get("r")
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write = self.dataset_mgr.get("w")
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self.assertEqual(len(read), 100)
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self.assertEqual(read, write)
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def test_ram_exec(self):
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self.execute(AD9910Exp, "ram_exec")
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ftw = self.dataset_mgr.get("ftw")
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self.assertEqual(ftw[0], ftw[1])
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self.assertEqual(ftw[2], ftw[3])
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