Sebastien Bourdeauducq 72c24ba320 identify_controller -> artiq_ctlid		2014-12-08 16:12:39 +08:00
..
Makefile	doc: add sphinx infrastructure	2014-09-18 17:45:54 +08:00
conf.py	manual: use theme options which looks like m-labs web site	2014-12-02 10:32:27 +08:00
core_drivers_reference.rst	doc: some precisions about controllers	2014-10-28 11:43:06 +08:00
core_language_reference.rst	doc/manual: minor fixes	2014-12-02 19:23:15 +08:00
drivers_reference.rst	manual/drivers_reference: add lda	2014-11-29 11:04:13 +08:00
fpga_board_ports.rst	targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG	2014-12-01 18:53:29 +08:00
getting_started.rst	artiq_run: reference module by filename	2014-12-08 16:11:31 +08:00
index.rst	doc/manual: add ports to index	2014-11-21 18:08:40 -08:00
installing.rst	switch to llvmlite	2014-12-05 17:05:43 +08:00
management_reference.rst	pc_rpc: document	2014-10-27 13:50:32 +08:00
writing_a_driver.rst	identify_controller -> artiq_ctlid	2014-12-08 16:12:39 +08:00