mirror of https://github.com/m-labs/artiq.git
274 lines
8.3 KiB
Python
274 lines
8.3 KiB
Python
from migen import *
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from migen.genlib.coding import PriorityEncoder
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from artiq.gateware.rtio import rtlink
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def _mk_edges(w, direction):
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l = [(1 << i) - 1 for i in range(w)]
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if direction == "rising":
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l = [2**w - 1 ^ x for x in l]
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elif direction == "falling":
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pass
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else:
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raise ValueError
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return l
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class _SerdesDriver(Module):
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def __init__(self, serdes_o, stb, data, fine_ts, override_en, override_o):
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previous_data = Signal()
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serdes_width = len(serdes_o)
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edges = Array(_mk_edges(serdes_width, "rising"))
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edges_n = Array(_mk_edges(serdes_width, "falling"))
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self.sync.rio_phy += [
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If(stb, previous_data.eq(data)),
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If(override_en,
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serdes_o.eq(Replicate(override_o, serdes_width))
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).Else(
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If(stb & ~previous_data & data,
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serdes_o.eq(edges[fine_ts]),
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).Elif(stb & previous_data & ~data,
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serdes_o.eq(edges_n[fine_ts]),
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).Else(
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serdes_o.eq(Replicate(previous_data, serdes_width)),
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)
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)
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]
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class Output(Module):
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def __init__(self, serdes):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(1, fine_ts_width=log2_int(len(serdes.o))))
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self.probes = [serdes.o[-1]]
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override_en = Signal()
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override_o = Signal()
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self.overrides = [override_en, override_o]
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# # #
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self.submodules += _SerdesDriver(
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serdes.o,
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self.rtlink.o.stb, self.rtlink.o.data, self.rtlink.o.fine_ts,
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override_en, override_o)
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class Inout(Module):
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def __init__(self, serdes):
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serdes_width = len(serdes.o)
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assert len(serdes.i) == serdes_width
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(2, 2, fine_ts_width=log2_int(serdes_width)),
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rtlink.IInterface(1, fine_ts_width=log2_int(serdes_width)))
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self.probes = [serdes.i[-1], serdes.oe]
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override_en = Signal()
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override_o = Signal()
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override_oe = Signal()
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self.overrides = [override_en, override_o, override_oe]
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# # #
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# Output
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self.submodules += _SerdesDriver(
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serdes_o=serdes.o,
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stb=self.rtlink.o.stb & (self.rtlink.o.address == 0),
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data=self.rtlink.o.data[0],
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fine_ts=self.rtlink.o.fine_ts,
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override_en=override_en, override_o=override_o)
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oe_k = Signal()
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self.sync.rio_phy += [
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If(self.rtlink.o.stb & (self.rtlink.o.address == 1),
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oe_k.eq(self.rtlink.o.data[0])),
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If(override_en,
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serdes.oe.eq(override_oe)
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).Else(
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serdes.oe.eq(oe_k)
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)
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]
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# Input
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sensitivity = Signal(2)
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self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
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sensitivity.eq(self.rtlink.o.data))
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i = serdes.i[-1]
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i_d = Signal()
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self.sync.rio_phy += [
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i_d.eq(i),
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self.rtlink.i.stb.eq(
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(sensitivity[0] & ( i & ~i_d)) |
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(sensitivity[1] & (~i & i_d))
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),
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self.rtlink.i.data.eq(i),
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]
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pe = PriorityEncoder(serdes_width)
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self.submodules += pe
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self.comb += pe.i.eq(serdes.i ^ Replicate(i_d, serdes_width))
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self.sync.rio_phy += self.rtlink.i.fine_ts.eq(pe.o)
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class _FakeSerdes(Module):
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def __init__(self):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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class _OutputTB(Module):
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def __init__(self):
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serdes = _FakeSerdes()
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self.submodules.dut = RenameClockDomains(Output(serdes),
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{"rio_phy": "sys"})
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def gen_simulation(self, selfp):
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 1
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selfp.dut.rtlink.o.stb = 1
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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selfp.dut.rtlink.o.data = 0
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selfp.dut.rtlink.o.fine_ts = 2
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selfp.dut.rtlink.o.stb = 1
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yield
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yield
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 7
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selfp.dut.rtlink.o.stb = 1
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for _ in range(6):
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# note that stb stays active; output should not change
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yield
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class _InoutTB(Module):
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def __init__(self):
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self.serdes = _FakeSerdes()
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self.submodules.dut = RenameClockDomains(Inout(self.serdes),
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{"rio_phy": "sys",
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"rio": "sys"})
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def check_input(self, selfp, stb, fine_ts=None):
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if stb != selfp.dut.rtlink.i.stb:
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print("KO rtlink.i.stb should be {} but is {}"
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.format(stb, selfp.dut.rtlink.i.stb))
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elif fine_ts is not None and fine_ts != selfp.dut.rtlink.i.fine_ts:
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print("KO rtlink.i.fine_ts should be {} but is {}"
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.format(fine_ts, selfp.dut.rtlink.i.fine_ts))
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else:
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print("OK")
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def check_output(self, selfp, data):
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if selfp.serdes.o != data:
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print("KO io.o should be {} but is {}".format(data, selfp.serdes.o))
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else:
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print("OK")
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def check_output_enable(self, selfp, oe):
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if selfp.serdes.oe != oe:
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print("KO io.oe should be {} but is {}".format(oe, selfp.serdes.oe))
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else:
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print("OK")
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def gen_simulation(self, selfp):
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selfp.dut.rtlink.o.address = 2
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selfp.dut.rtlink.o.data = 0b11
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selfp.dut.rtlink.o.stb = 1 # set sensitivity to rising + falling
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yield
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selfp.dut.rtlink.o.stb = 0
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self.check_output_enable(selfp, 0)
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yield
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selfp.serdes.i = 0b11111110 # rising edge at fine_ts = 1
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yield
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selfp.serdes.i = 0b11111111
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yield
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self.check_input(selfp, stb=1, fine_ts=1)
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selfp.serdes.i = 0b01111111 # falling edge at fine_ts = 7
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yield
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selfp.serdes.i = 0b00000000
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yield
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self.check_input(selfp, stb=1, fine_ts=7)
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selfp.serdes.i = 0b11000000 # rising edge at fine_ts = 6
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yield
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selfp.serdes.i = 0b11111111
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yield
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self.check_input(selfp, stb=1, fine_ts=6)
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selfp.dut.rtlink.o.address = 2
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selfp.dut.rtlink.o.data = 0b11
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selfp.dut.rtlink.o.stb = 1 # set sensitivity to rising only
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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selfp.serdes.i = 0b00001111 # falling edge at fine_ts = 4
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yield
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self.check_input(selfp, stb=0) # no strobe, sensitivity is rising edge
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selfp.serdes.i = 0b11110000 # rising edge at fine_ts = 4
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yield
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self.check_input(selfp, stb=1, fine_ts=4)
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selfp.dut.rtlink.o.address = 1
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.stb = 1 # set Output Enable to 1
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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yield
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self.check_output_enable(selfp, 1)
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selfp.dut.rtlink.o.address = 0
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 3
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selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 3
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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self.check_output(selfp, data=0b11111000)
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yield
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self.check_output(selfp, data=0xFF) # stays at 1
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selfp.dut.rtlink.o.data = 0
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selfp.dut.rtlink.o.fine_ts = 0
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selfp.dut.rtlink.o.stb = 1 # falling edge at fine_ts = 0
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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self.check_output(selfp, data=0)
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yield
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self.check_output(selfp, data=0)
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 7
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selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 7
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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self.check_output(selfp, data=0b10000000)
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if __name__ == "__main__":
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import sys
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from migen.sim.generic import Simulator, TopLevel
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if len(sys.argv) != 2:
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print("Incorrect command line")
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sys.exit(1)
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cls = {
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"output": _OutputTB,
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"inout": _InoutTB
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}[sys.argv[1]]
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with Simulator(cls(), TopLevel("top.vcd", clk_period=int(1/0.125))) as s:
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s.run()
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