mirror of https://github.com/m-labs/artiq.git
71 lines
2.5 KiB
Python
71 lines
2.5 KiB
Python
from migen import *
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from artiq.gateware.rtio.phy import ttl_serdes_generic
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class _OSERDESE2_8X(Module):
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def __init__(self, pad):
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self.o = Signal(8)
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self.t_in = Signal()
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self.t_out = Signal()
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# # #
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o = self.o
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self.specials += Instance("OSERDESE2",
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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o_OQ=pad, o_TQ=self.t_out,
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i_CLK=ClockSignal("rtiox4"),
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i_CLKDIV=ClockSignal("rio_phy"),
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i_D1=o[0], i_D2=o[1], i_D3=o[2], i_D4=o[3],
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i_D5=o[4], i_D6=o[5], i_D7=o[6], i_D8=o[7],
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i_TCE=1, i_OCE=1, i_RST=0,
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i_T1=self.t_in)
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class _IOSERDESE2_8X(Module):
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def __init__(self, pad):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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# # #
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pad_i = Signal()
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pad_o = Signal()
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i = self.i
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self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
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p_DATA_WIDTH=8,
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p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
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o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
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o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
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i_D=pad_i,
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i_CLK=ClockSignal("rtiox4"),
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i_CLKB=~ClockSignal("rtiox4"),
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i_CE1=1, i_RST=0,
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i_CLKDIV=ClockSignal("rio_phy"))
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oserdes = _OSERDESE2_8X(pad_o)
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self.submodules += oserdes
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self.specials += Instance("IOBUF",
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i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
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io_IO=pad)
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self.comb += [
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oserdes.t_in.eq(~self.oe),
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oserdes.o.eq(self.o)
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]
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class Output_8X(ttl_serdes_generic.Output):
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def __init__(self, pad):
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serdes = _OSERDESE2_8X(pad)
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self.submodules += serdes
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ttl_serdes_generic.Output.__init__(self, serdes)
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class Inout_8X(ttl_serdes_generic.Inout):
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def __init__(self, pad):
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serdes = _IOSERDESE2_8X(pad)
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self.submodules += serdes
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ttl_serdes_generic.Inout.__init__(self, serdes)
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