mirror of https://github.com/m-labs/artiq.git
95 lines
4.1 KiB
Python
95 lines
4.1 KiB
Python
from migen.build.generic_platform import *
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papilio_adapter_io = [
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("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
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# to feed the 125 MHz clock (preferrably from DDS SYNC_CLK)
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# to the FPGA, use the xtrig pair.
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#
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# on papiliopro-adapter, xtrig (C:12) is connected to a GCLK
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#
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# on pipistrello, C:15 is the only GCLK in proximity, used as a button
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# input, BTN2/PMT2 in papiliopro-adapter
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# either improve the DDS box to feed 125MHz into the PMT2 pair, or:
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#
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# * disconnect C:15 from its periphery on the adapter board
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# * bridge C:15 to the xtrig output of the transciever
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# * optionally, disconnect C:12 from its periphery
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
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("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
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("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
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("pmt", 2, Pins("C:15"), IOStandard("LVTTL")), # rarely equipped
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("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
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("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
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("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
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("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
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("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
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("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
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("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
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("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
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("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
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("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
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("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
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("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud_n", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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fmc_adapter_io = [
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("pmt", 0, Pins("LPC:LA20_N"), IOStandard("LVTTL")),
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("pmt", 1, Pins("LPC:LA24_P"), IOStandard("LVTTL")),
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("ttl", 0, Pins("LPC:LA21_P"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA25_P"), IOStandard("LVTTL")),
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("ttl", 2, Pins("LPC:LA21_N"), IOStandard("LVTTL")),
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("ttl", 3, Pins("LPC:LA25_N"), IOStandard("LVTTL")),
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("ttl", 4, Pins("LPC:LA22_P"), IOStandard("LVTTL")),
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("ttl", 5, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
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("ttl", 6, Pins("LPC:LA22_N"), IOStandard("LVTTL")),
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("ttl", 7, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
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("ttl", 8, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
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("ttl", 9, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 10, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
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("ttl", 11, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
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("ttl", 12, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 13, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("LPC:LA11_P"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("LPC:LA04_N LPC:LA14_N LPC:LA05_P LPC:LA15_P "
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"LPC:LA05_N LPC:LA15_N")),
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Subsignal("d", Pins("LPC:LA06_P LPC:LA16_P LPC:LA06_N LPC:LA16_N "
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"LPC:LA07_P LPC:LA17_CC_P LPC:LA07_N "
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"LPC:LA17_CC_N")),
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Subsignal("sel", Pins("LPC:LA12_N LPC:LA03_P LPC:LA13_P LPC:LA03_N "
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"LPC:LA13_N")),
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Subsignal("p", Pins("LPC:LA11_N LPC:LA02_P")),
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Subsignal("fud_n", Pins("LPC:LA14_P")),
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Subsignal("wr_n", Pins("LPC:LA04_P")),
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Subsignal("rd_n", Pins("LPC:LA02_N")),
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Subsignal("rst_n", Pins("LPC:LA12_P")),
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IOStandard("LVTTL")),
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]
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