Robert Jördens 8f54a1e619 pipistrello: sys_clk 83 -> 75 MHz ... This should close #341 once migen generates stable output.		2016-03-21 13:47:32 +01:00
..
__init__.py	package everything to rebuild core device binaries	2015-11-09 10:47:14 +08:00
kc705.py	targets/kc705/qc2: hook up HPC backplane	2016-03-16 16:19:56 +08:00
pipistrello.py	pipistrello: sys_clk 83 -> 75 MHz	2016-03-21 13:47:32 +01:00