mirror of https://github.com/m-labs/artiq.git
428 lines
15 KiB
Rust
428 lines
15 KiB
Rust
mod clock_mux {
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use board_misoc::csr;
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const CLK_SRC_EXT_SEL : u8 = 1 << 0;
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const REF_CLK_SRC_SEL : u8 = 1 << 1;
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const DAC_CLK_SRC_SEL : u8 = 1 << 2;
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const REF_LO_CLK_SEL : u8 = 1 << 3;
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pub fn init() {
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unsafe {
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csr::clock_mux::out_write(
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1*CLK_SRC_EXT_SEL | // use ext clk from sma
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1*REF_CLK_SRC_SEL |
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1*DAC_CLK_SRC_SEL |
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0*REF_LO_CLK_SEL);
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}
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}
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}
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mod hmc830 {
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use board_misoc::{csr, clock};
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fn spi_setup() {
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unsafe {
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while csr::converter_spi::idle_read() == 0 {}
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csr::converter_spi::offline_write(0);
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csr::converter_spi::end_write(1);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(0);
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csr::converter_spi::length_write(32 - 1);
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csr::converter_spi::div_write(16 - 2);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC830_CS);
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}
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}
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pub fn select_spi_mode() {
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spi_setup();
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unsafe {
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// rising egde on CS since cs_polarity still 0
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// selects "HMC Mode"
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// do a dummy cycle with cs still high to clear CS
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csr::converter_spi::length_write(0);
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csr::converter_spi::data_write(0);
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::length_write(32 - 1);
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}
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}
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fn write(addr: u8, data: u32) {
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let val = ((addr as u32) << 24) | data;
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(val << 1); // last clk cycle loads data
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}
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}
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fn read(addr: u8) -> u32 {
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// SDO (miso/read bits) is technically CPHA=1, while SDI is CPHA=0
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// trust that the 8.2ns+0.2ns/pF provide enough hold time on top of
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// the SPI round trip delay and stick with CPHA=0
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write((1 << 6) | addr, 0);
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_read() & 0xffffff
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}
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}
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pub fn detect() -> Result<(), &'static str> {
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spi_setup();
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let id = read(0x00);
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if id != 0xa7975 {
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error!("invalid HMC830 ID: 0x{:08x}", id);
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return Err("invalid HMC830 identification");
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} else {
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info!("HMC830 found");
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}
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Ok(())
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}
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pub fn init() {
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// Configure HMC830 for integer-N operation
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// See "PLLs with integrated VCO- RF Applications Product & Operating
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// Guide"
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spi_setup();
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info!("loading HMC830 configuration...");
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write(0x0, 0x20); // software reset
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write(0x0, 0x00); // normal operation
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write(0x6, 0x307ca); // integer-N mode (NB data sheet table 5.8 not self-consistent)
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write(0x7, 0x4d); // digital lock detect, 1/2 cycle window (6.5ns window)
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write(0x9, 0x2850); // charge pump: 1.6mA, no offset
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write(0xa, 0x2045); // for wideband devices like the HMC830
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write(0xb, 0x7c061); // for HMC830
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// VCO subsystem registers
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// NB software reset does not seem to reset these registers, so always
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// program them all!
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write(0x5, 0xf88); // 1: defaults
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write(0x5, 0x6010); // 2: mute output until output divider set
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write(0x5, 0x2818); // 3: wideband PLL defaults
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write(0x5, 0x60a0); // 4: HMC830 magic value
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write(0x5, 0x1628); // 5: HMC830 magic value
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write(0x5, 0x7fb0); // 6: HMC830 magic value
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write(0x5, 0x0); // ready for VCO auto-cal
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info!(" ...done");
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}
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pub fn set_dividers(r_div: u32, n_div: u32, m_div: u32, out_div: u32) {
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// VCO frequency: f_vco = (f_ref/r_div)*(n_int + n_frac/2**24)
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// VCO frequency range [1.5GHz, 3GHz]
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// Output frequency: f_out = f_vco/out_div
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// Max PFD frequency: 125MHz for integer-N, 100MHz for fractional
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// (mode B)
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// Max reference frequency: 350MHz, however f_ref >= 200MHz requires
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// setting 0x08[21]=1
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//
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// :param r_div: reference divider [1, 16383]
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// :param n_div: VCO divider, integer part. Integer-N mode: [16, 2**19-1]
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// fractional mode: [20, 2**19-4]
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// :param m_div: VCO divider, fractional part [0, 2**24-1]
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// :param out_div: output divider [1, 62] (0 mutes output)
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info!("setting HMC830 dividers...");
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write(0x5, 0x6010 + (out_div << 7) + (((out_div <= 2) as u32) << 15));
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write(0x5, 0x0); // ready for VCO auto-cal
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write(0x2, r_div);
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write(0x4, m_div);
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write(0x3, n_div);
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info!(" ...done");
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}
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pub fn check_locked() -> Result<(), &'static str> {
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info!("waiting for HMC830 lock...");
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let t = clock::get_ms();
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while read(0x12) & 0x02 == 0 {
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if clock::get_ms() > t + 2000 {
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error!("lock timeout. Register dump:");
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for addr in 0x00..0x14 {
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// These registers don't exist (in the data sheet at least)
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if addr == 0x0d || addr == 0x0e { continue; }
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error!(" [0x{:02x}] = 0x{:04x}", addr, read(addr));
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}
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return Err("lock timeout");
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}
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}
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info!(" ...locked");
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Ok(())
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}
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}
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pub mod hmc7043 {
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use board_misoc::{csr, clock};
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// All frequencies assume 1.2GHz HMC830 output
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const DAC_CLK_DIV: u32 = 2; // 600MHz
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const FPGA_CLK_DIV: u32 = 8; // 150MHz
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const SYSREF_DIV: u32 = 128; // 9.375MHz
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const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
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// enabled, divider, output config
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const OUTPUT_CONFIG: [(bool, u32, u8); 14] = [
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(true, DAC_CLK_DIV, 0x08), // 0: DAC2_CLK
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(true, SYSREF_DIV, 0x08), // 1: DAC2_SYSREF
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(true, DAC_CLK_DIV, 0x08), // 2: DAC1_CLK
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(true, SYSREF_DIV, 0x08), // 3: DAC1_SYSREF
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(false, 0, 0x08), // 4: ADC2_CLK
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(false, 0, 0x08), // 5: ADC2_SYSREF
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(true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2
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(true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS
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(true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1
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(false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK
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(false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK
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(false, 0, 0x10), // 11: FPGA_ADC_SYSREF, LVDS
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(false, 0, 0x08), // 12: ADC1_CLK
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(false, 0, 0x08), // 13: ADC1_SYSREF
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];
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fn spi_setup() {
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unsafe {
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while csr::converter_spi::idle_read() == 0 {}
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csr::converter_spi::offline_write(0);
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csr::converter_spi::end_write(1);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(0); // change mid-transaction for reads
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csr::converter_spi::length_write(24 - 1);
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csr::converter_spi::div_write(16 - 2);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC7043_CS);
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}
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}
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fn write(addr: u16, data: u8) {
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let cmd = (0 << 15) | addr;
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let val = ((cmd as u32) << 8) | data as u32;
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(val << 8);
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}
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}
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fn read(addr: u16) -> u8 {
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let cmd = (1 << 15) | addr;
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let val = cmd as u32;
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::end_write(0);
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csr::converter_spi::length_write(16 - 1);
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csr::converter_spi::data_write(val << 16);
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::end_write(1);
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csr::converter_spi::half_duplex_write(1);
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csr::converter_spi::length_write(8 - 1);
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csr::converter_spi::data_write(0);
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::half_duplex_write(0);
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csr::converter_spi::length_write(24 - 1);
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csr::converter_spi::data_read() as u8
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}
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}
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pub const CHIP_ID: u32 = 0xf17904;
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pub fn get_id() -> u32 {
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spi_setup();
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(read(0x78) as u32) << 16 | (read(0x79) as u32) << 8 | read(0x7a) as u32
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}
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pub fn detect() -> Result<(), &'static str> {
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let id = get_id();
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if id != CHIP_ID {
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error!("invalid HMC7043 ID: 0x{:08x}", id);
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return Err("invalid HMC7043 identification");
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} else {
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info!("HMC7043 found");
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}
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Ok(())
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}
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pub fn enable() {
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info!("enabling HMC7043");
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unsafe {
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csr::hmc7043_reset::out_write(0);
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}
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clock::spin_us(10_000);
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spi_setup();
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write(0x0, 0x1); // Software reset
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write(0x0, 0x0); // Normal operation
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write(0x1, 0x48); // mute all outputs
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}
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pub fn init() {
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spi_setup();
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info!("loading configuration...");
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write(0xA, 0x06); // Disable the REFSYNCIN input
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write(0xB, 0x07); // Enable the CLKIN input as LVPECL
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write(0x50, 0x1f); // Disable GPO pin
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write(0x9F, 0x4d); // Unexplained high-performance mode
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write(0xA0, 0xdf); // Unexplained high-performance mode
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// Enable required output groups
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write(0x4, (1 << 0) |
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(1 << 1) |
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(1 << 3) |
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(1 << 4));
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write(0x5c, (HMC_SYSREF_DIV & 0xff) as u8); // Set SYSREF timer divider
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write(0x5d, ((HMC_SYSREF_DIV & 0x0f) >> 8) as u8);
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for channel in 0..OUTPUT_CONFIG.len() {
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let channel_base = 0xc8 + 0x0a*(channel as u16);
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let (enabled, divider, outcfg) = OUTPUT_CONFIG[channel];
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if enabled {
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if channel % 2 == 0 {
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// DCLK channel: enable high-performance mode
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write(channel_base, 0xd1);
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} else {
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// SYSREF channel: disable hi-perf mode, enable slip
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write(channel_base, 0x71);
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}
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} else {
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write(channel_base, 0x10);
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}
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write(channel_base + 0x1, (divider & 0xff) as u8);
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write(channel_base + 0x2, ((divider & 0x0f) >> 8) as u8);
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// bypass analog phase shift on DCLK channels to reduce noise
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if channel % 2 == 0 {
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if divider != 0 {
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write(channel_base + 0x7, 0x00); // enable divider
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} else {
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write(channel_base + 0x7, 0x03); // bypass divider for lowest noise
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}
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} else {
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write(channel_base + 0x7, 0x01);
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}
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write(channel_base + 0x8, outcfg)
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}
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write(0x1, 0x4a); // Reset dividers and FSMs
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write(0x1, 0x48);
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write(0x1, 0xc8); // Synchronize dividers
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write(0x1, 0x40); // Unmute, high-performance/low-noise mode
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info!(" ...done");
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}
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pub fn sysref_offset_dac(dacno: u8, phase_offset: u16) {
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/* Analog delay resolution: 25ps
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* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
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* 16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
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*/
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let analog_delay = (phase_offset % 17) as u8;
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let digital_delay = (phase_offset / 17) as u8;
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spi_setup();
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if dacno == 0 {
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write(0x00d5, analog_delay);
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write(0x00d6, digital_delay);
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} else if dacno == 1 {
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write(0x00e9, analog_delay);
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write(0x00ea, digital_delay);
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} else {
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unimplemented!();
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}
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}
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fn sysref_offset_fpga(phase_offset: u16) {
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let analog_delay = (phase_offset % 17) as u8;
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let digital_delay = (phase_offset / 17) as u8;
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spi_setup();
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write(0x0111, analog_delay);
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write(0x0112, digital_delay);
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}
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fn sysref_slip() {
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spi_setup();
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write(0x0002, 0x02);
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write(0x0002, 0x00);
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}
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fn sysref_sample() -> bool {
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unsafe { csr::sysref_sampler::sample_result_read() == 1 }
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}
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pub fn sysref_rtio_align(phase_offset: u16) {
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info!("aligning SYSREF with RTIO...");
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let mut slips0 = 0;
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let mut slips1 = 0;
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// meet setup/hold (assuming FPGA timing margins are OK)
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sysref_offset_fpga(phase_offset);
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// if we are already in the 1 zone, get out of it
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while sysref_sample() {
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sysref_slip();
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slips0 += 1;
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}
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// get to the edge of the 0->1 transition (our final setpoint)
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while !sysref_sample() {
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sysref_slip();
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slips1 += 1;
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}
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info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1);
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let mut margin_plus = None;
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for d in 0..phase_offset {
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sysref_offset_fpga(phase_offset - d);
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if !sysref_sample() {
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margin_plus = Some(d);
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break;
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}
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}
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// meet setup/hold
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sysref_offset_fpga(phase_offset);
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if margin_plus.is_some() {
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let margin_plus = margin_plus.unwrap();
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// one phase slip (period of the 1.2GHz input clock)
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let period = 2*17; // approximate: 2 digital coarse delay steps
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let margin_minus = if period > margin_plus { period - margin_plus } else { 0 };
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info!(" margin at FPGA: -{} +{}", margin_minus, margin_plus);
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if margin_minus < 10 || margin_plus < 10 {
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error!("SYSREF margin at FPGA is too small");
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}
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} else {
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error!("unable to determine SYSREF margin at FPGA");
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}
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}
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}
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pub fn init() -> Result<(), &'static str> {
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clock_mux::init();
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/* do not use other SPI devices before HMC830 SPI mode selection */
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hmc830::select_spi_mode();
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hmc830::detect()?;
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hmc830::init();
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// 1.2GHz out
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#[cfg(hmc830_ref = "100")]
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hmc830::set_dividers(1, 24, 0, 2);
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#[cfg(hmc830_ref = "150")]
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hmc830::set_dividers(2, 32, 0, 2);
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hmc830::check_locked()?;
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if hmc7043::get_id() == hmc7043::CHIP_ID {
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error!("HMC7043 detected while in reset (board rework missing?)");
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}
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hmc7043::enable();
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hmc7043::detect()?;
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hmc7043::init();
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Ok(())
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}
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