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338 lines
13 KiB
Python
338 lines
13 KiB
Python
"""
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Driver for the AD9914 DDS (with parallel bus) on RTIO.
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"""
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from artiq.language.core import *
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from artiq.language.types import *
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from artiq.language.units import *
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from artiq.coredevice.rtio import rtio_output
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from numpy import int32, int64
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__all__ = [
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"AD9914",
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"PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE", "PHASE_MODE_TRACKING"
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]
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_PHASE_MODE_DEFAULT = -1
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PHASE_MODE_CONTINUOUS = 0
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PHASE_MODE_ABSOLUTE = 1
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PHASE_MODE_TRACKING = 2
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AD9914_REG_CFR1L = 0x01
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AD9914_REG_CFR1H = 0x03
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AD9914_REG_CFR2L = 0x05
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AD9914_REG_CFR2H = 0x07
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AD9914_REG_CFR3L = 0x09
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AD9914_REG_CFR3H = 0x0b
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AD9914_REG_CFR4L = 0x0d
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AD9914_REG_CFR4H = 0x0f
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AD9914_REG_DRGFL = 0x11
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AD9914_REG_DRGFH = 0x13
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AD9914_REG_DRGBL = 0x15
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AD9914_REG_DRGBH = 0x17
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AD9914_REG_DRGAL = 0x19
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AD9914_REG_DRGAH = 0x1b
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AD9914_REG_POW = 0x31
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AD9914_REG_ASF = 0x33
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AD9914_REG_USR0 = 0x6d
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AD9914_FUD = 0x80
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AD9914_GPIO = 0x81
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class AD9914:
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"""Driver for one AD9914 DDS channel.
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The time cursor is not modified by any function in this class.
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Output event replacement is not supported and issuing commands at the same
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time is an error.
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:param sysclk: DDS system frequency. The DDS system clock must be a
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phase-locked multiple of the RTIO clock.
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:param bus_channel: RTIO channel number of the DDS bus.
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:param channel: channel number (on the bus) of the DDS device to control.
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"""
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kernel_invariants = {"core", "sysclk", "bus_channel", "channel",
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"rtio_period_mu", "sysclk_per_mu", "write_duration_mu",
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"dac_cal_duration_mu", "init_duration_mu", "init_sync_duration_mu",
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"set_duration_mu", "set_x_duration_mu", "exit_x_duration_mu"}
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def __init__(self, dmgr, sysclk, bus_channel, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.sysclk = sysclk
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self.bus_channel = bus_channel
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self.channel = channel
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self.phase_mode = PHASE_MODE_CONTINUOUS
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self.rtio_period_mu = int64(8)
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self.sysclk_per_mu = int32(self.sysclk * self.core.ref_period)
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self.write_duration_mu = 5 * self.rtio_period_mu
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self.dac_cal_duration_mu = 147000 * self.rtio_period_mu
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self.init_duration_mu = 13 * self.write_duration_mu + self.dac_cal_duration_mu
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self.init_sync_duration_mu = 21 * self.write_duration_mu + 2 * self.dac_cal_duration_mu
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self.set_duration_mu = 7 * self.write_duration_mu
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self.set_x_duration_mu = 7 * self.write_duration_mu
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self.exit_x_duration_mu = 3 * self.write_duration_mu
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@kernel
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def write(self, addr, data):
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rtio_output((self.bus_channel << 8) | addr, data)
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delay_mu(self.write_duration_mu)
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@kernel
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def init(self):
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"""Resets and initializes the DDS channel.
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this purpose.
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"""
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delay_mu(-self.init_duration_mu)
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self.write(AD9914_GPIO, (1 << self.channel) << 1);
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# Note another undocumented "feature" of the AD9914:
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# Programmable modulus breaks if the digital ramp enable bit is
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# not set at the same time.
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self.write(AD9914_REG_CFR1H, 0x0000) # Enable cosine output
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self.write(AD9914_REG_CFR2L, 0x8900) # Enable matched latency
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self.write(AD9914_REG_CFR2H, 0x0089) # Enable profile mode + programmable modulus + DRG
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self.write(AD9914_REG_DRGAL, 0) # Programmable modulus A = 0
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self.write(AD9914_REG_DRGAH, 0)
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self.write(AD9914_REG_DRGBH, 0x8000) # Programmable modulus B == 2**31
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self.write(AD9914_REG_DRGBL, 0x0000)
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self.write(AD9914_REG_ASF, 0x0fff) # Set amplitude to maximum
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self.write(AD9914_REG_CFR4H, 0x0105) # Enable DAC calibration
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self.write(AD9914_FUD, 0)
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delay_mu(self.dac_cal_duration_mu)
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self.write(AD9914_REG_CFR4H, 0x0005) # Disable DAC calibration
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self.write(AD9914_FUD, 0)
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@kernel
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def init_sync(self, sync_delay):
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"""Resets and initializes the DDS channel as well as configures
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the AD9914 DDS for synchronisation. The synchronisation procedure
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follows the steps outlined in the AN-1254 application note.
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this.
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This function cannot be used in a batch; the correct way of
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initializing multiple DDS channels is to call this function
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sequentially with a delay between the calls. 10ms provides a good
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timing margin.
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:param sync_delay: integer from 0 to 0x3f that sets the value of
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SYNC_OUT (bits 3-5) and SYNC_IN (bits 0-2) delay ADJ bits.
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"""
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delay_mu(-self.init_sync_duration_mu)
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self.write(AD9914_GPIO, (1 << self.channel) << 1)
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self.write(AD9914_REG_CFR4H, 0x0105) # Enable DAC calibration
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self.write(AD9914_FUD, 0)
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delay_mu(self.dac_cal_duration_mu)
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self.write(AD9914_REG_CFR4H, 0x0005) # Disable DAC calibration
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self.write(AD9914_FUD, 0)
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self.write(AD9914_REG_CFR2L, 0x8b00) # Enable matched latency and sync_out
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self.write(AD9914_FUD, 0)
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# Set cal with sync and set sync_out and sync_in delay
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self.write(AD9914_REG_USR0, 0x0840 | (sync_delay & 0x3f))
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self.write(AD9914_FUD, 0)
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self.write(AD9914_REG_CFR4H, 0x0105) # Enable DAC calibration
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self.write(AD9914_FUD, 0)
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delay_mu(self.dac_cal_duration_mu)
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self.write(AD9914_REG_CFR4H, 0x0005) # Disable DAC calibration
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self.write(AD9914_FUD, 0)
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self.write(AD9914_REG_CFR1H, 0x0000) # Enable cosine output
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self.write(AD9914_REG_CFR2H, 0x0089) # Enable profile mode + programmable modulus + DRG
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self.write(AD9914_REG_DRGAL, 0) # Programmable modulus A = 0
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self.write(AD9914_REG_DRGAH, 0)
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self.write(AD9914_REG_DRGBH, 0x8000) # Programmable modulus B == 2**31
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self.write(AD9914_REG_DRGBL, 0x0000)
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self.write(AD9914_REG_ASF, 0x0fff) # Set amplitude to maximum
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self.write(AD9914_FUD, 0)
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@kernel
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def set_phase_mode(self, phase_mode):
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"""Sets the phase mode of the DDS channel. Supported phase modes are:
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* :const:`PHASE_MODE_CONTINUOUS`: the phase accumulator is unchanged when
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switching frequencies. The DDS phase is the sum of the phase
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accumulator and the phase offset. The only discrete jumps in the
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DDS output phase come from changes to the phase offset.
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* :const:`PHASE_MODE_ABSOLUTE`: the phase accumulator is reset when
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switching frequencies. Thus, the phase of the DDS at the time of
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the frequency change is equal to the phase offset.
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* :const:`PHASE_MODE_TRACKING`: when switching frequencies, the phase
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accumulator is set to the value it would have if the DDS had been
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running at the specified frequency since the start of the
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experiment.
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.. warning:: This setting may become inconsistent when used as part of
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a DMA recording. When using DMA, it is recommended to specify the
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phase mode explicitly when calling :meth:`set` or :meth:`set_mu`.
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"""
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self.phase_mode = phase_mode
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@kernel
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def set_mu(self, ftw, pow=0, phase_mode=_PHASE_MODE_DEFAULT,
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asf=0x0fff, ref_time_mu=-1):
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"""Sets the DDS channel to the specified frequency and phase.
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This uses machine units (FTW and POW). The frequency tuning word width
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is 32, the phase offset word width is 16, and the amplitude scale factor
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width is 12.
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The "frequency update" pulse is sent to the DDS with a fixed latency
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with respect to the current position of the time cursor.
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:param ftw: frequency to generate.
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:param pow: adds an offset to the phase.
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:param phase_mode: if specified, overrides the default phase mode set
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by :meth:`set_phase_mode` for this call.
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:param ref_time_mu: reference time used to compute phase. Specifying this
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makes it easier to have a well-defined phase relationship between
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DDSes on the same bus that are updated at a similar time.
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:return: Resulting phase offset word after application of phase
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tracking offset. When using :const:`PHASE_MODE_CONTINUOUS` in
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subsequent calls, use this value as the "current" phase.
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"""
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if phase_mode == _PHASE_MODE_DEFAULT:
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phase_mode = self.phase_mode
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if ref_time_mu < 0:
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ref_time_mu = now_mu()
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delay_mu(-self.set_duration_mu)
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self.write(AD9914_GPIO, (1 << self.channel) << 1)
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self.write(AD9914_REG_DRGFL, ftw & 0xffff)
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self.write(AD9914_REG_DRGFH, (ftw >> 16) & 0xffff)
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# We need the RTIO fine timestamp clock to be phase-locked
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# to DDS SYSCLK, and divided by an integer self.sysclk_per_mu.
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if phase_mode == PHASE_MODE_CONTINUOUS:
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# Do not clear phase accumulator on FUD
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# Disable autoclear phase accumulator and enables OSK.
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self.write(AD9914_REG_CFR1L, 0x0108)
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else:
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# Clear phase accumulator on FUD
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# Enable autoclear phase accumulator and enables OSK.
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self.write(AD9914_REG_CFR1L, 0x2108)
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fud_time = now_mu() + 2 * self.write_duration_mu
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pow -= int32((ref_time_mu - fud_time) * self.sysclk_per_mu * ftw >> (32 - 16))
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if phase_mode == PHASE_MODE_TRACKING:
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pow += int32(ref_time_mu * self.sysclk_per_mu * ftw >> (32 - 16))
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self.write(AD9914_REG_POW, pow)
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self.write(AD9914_REG_ASF, asf)
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self.write(AD9914_FUD, 0)
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return pow
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return round(float(int64(2)**32*frequency/self.sysclk))
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@portable(flags={"fast-math"})
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def ftw_to_frequency(self, ftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word.
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"""
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return ftw*self.sysclk/int64(2)**32
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@portable(flags={"fast-math"})
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def turns_to_pow(self, turns):
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"""Returns the phase offset word corresponding to the given phase
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in turns."""
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return round(float(turns*2**16))
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@portable(flags={"fast-math"})
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def pow_to_turns(self, pow):
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"""Returns the phase in turns corresponding to the given phase offset
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word."""
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return pow/2**16
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@portable(flags={"fast-math"})
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def amplitude_to_asf(self, amplitude):
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"""Returns amplitude scale factor corresponding to given amplitude."""
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return round(float(amplitude*0x0fff))
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@portable(flags={"fast-math"})
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def asf_to_amplitude(self, asf):
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"""Returns the amplitude corresponding to the given amplitude scale
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factor."""
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return asf/0x0fff
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@kernel
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def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT,
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amplitude=1.0):
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"""Like :meth:`set_mu`, but uses Hz and turns."""
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return self.pow_to_turns(
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self.set_mu(self.frequency_to_ftw(frequency),
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self.turns_to_pow(phase), phase_mode,
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self.amplitude_to_asf(amplitude)))
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# Extended-resolution functions
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@kernel
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def set_x_mu(self, xftw, amplitude=0x0fff):
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"""Set the DDS frequency and amplitude with an extended-resolution
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(63-bit) frequency tuning word.
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Phase control is not implemented in this mode; the phase offset
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can assume any value.
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After this function has been called, exit extended-resolution mode
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before calling functions that use standard-resolution mode.
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"""
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delay_mu(-self.set_x_duration_mu)
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self.write(AD9914_GPIO, (1 << self.channel) << 1)
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self.write(AD9914_REG_DRGAL, xftw & 0xffff)
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self.write(AD9914_REG_DRGAH, (xftw >> 16) & 0x7fff)
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self.write(AD9914_REG_DRGFL, (xftw >> 31) & 0xffff)
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self.write(AD9914_REG_DRGFH, (xftw >> 47) & 0xffff)
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self.write(AD9914_REG_ASF, amplitude)
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self.write(AD9914_FUD, 0)
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@kernel
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def exit_x(self):
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"""Exits extended-resolution mode."""
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delay_mu(-self.exit_x_duration_mu)
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self.write(AD9914_GPIO, (1 << self.channel) << 1)
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self.write(AD9914_REG_DRGAL, 0)
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self.write(AD9914_REG_DRGAH, 0)
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@portable(flags={"fast-math"})
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def frequency_to_xftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency (extended resolution mode).
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"""
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return int64(round(2.0*float(int64(2)**62)*frequency/self.sysclk))
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@portable(flags={"fast-math"})
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def xftw_to_frequency(self, xftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word (extended resolution mode).
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"""
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return xftw*self.sysclk/(2.0*float(int64(2)**62))
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@kernel
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def set_x(self, frequency, amplitude=1.0):
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"""Like :meth:`set_x_mu`, but uses Hz and turns.
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Note that the precision of ``float`` is less than the precision
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of the extended frequency tuning word.
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"""
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self.set_x_mu(self.frequency_to_xftw(frequency),
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self.amplitude_to_asf(amplitude))
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