mirror of
https://github.com/m-labs/artiq.git
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196 lines
4.0 KiB
Python
196 lines
4.0 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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class AD9858(Module):
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"""Wishbone interface to the AD9858 DDS chip.
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Addresses 0-63 map the AD9858 registers.
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Data is zero-padded.
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Write to address 64 to pulse the FUD signal.
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Address 65 is a GPIO register that controls the sel, p and reset signals.
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sel is mapped to the lower bits, followed by p and reset.
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Write timing:
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Address is set one cycle before assertion of we_n.
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we_n is asserted for one cycle, at the same time as valid data is driven.
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Read timing:
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Address is set one cycle before assertion of rd_n.
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rd_n is asserted for 3 cycles.
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Data is sampled 2 cycles into the assertion of rd_n.
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Design:
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All IO pads are registered.
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LVDS driver/receiver propagation delays are 3.6+4.5 ns max
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LVDS state transition delays are 20, 15 ns max
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Schmitt trigger delays are 6.4ns max
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Round-trip addr A setup (> RX, RD, D to Z), RD prop, D valid (< D
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valid), D prop is ~15 + 10 + 20 + 10 = 55ns
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"""
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def __init__(self, pads, bus=None):
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if bus is None:
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bus = wishbone.Interface()
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self.bus = bus
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###
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dts = TSTriple(8)
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self.specials += dts.get_tristate(pads.d)
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dr = Signal(8)
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rx = Signal()
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self.sync += [
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pads.a.eq(bus.adr),
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dts.o.eq(bus.dat_w),
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dr.eq(dts.i),
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dts.oe.eq(~rx)
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]
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gpio = Signal(flen(pads.sel) + flen(pads.p) + 1)
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gpio_load = Signal()
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self.sync += If(gpio_load, gpio.eq(bus.dat_w))
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self.comb += [
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Cat(pads.sel, pads.p).eq(gpio),
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pads.rst_n.eq(~gpio[-1]),
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]
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bus_r_gpio = Signal()
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self.comb += If(bus_r_gpio,
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bus.dat_r.eq(gpio)
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).Else(
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bus.dat_r.eq(dr)
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)
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fud = Signal()
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self.sync += pads.fud_n.eq(~fud)
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pads.wr_n.reset = 1
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pads.rd_n.reset = 1
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wr = Signal()
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rd = Signal()
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self.sync += pads.wr_n.eq(~wr), pads.rd_n.eq(~rd)
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fsm = FSM("IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(bus.cyc & bus.stb,
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If(bus.adr[6],
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If(bus.adr[0],
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NextState("GPIO")
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).Else(
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NextState("FUD")
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)
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).Else(
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If(bus.we,
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NextState("WRITE")
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).Else(
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NextState("READ")
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)
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)
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)
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)
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fsm.act("WRITE",
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# 3ns A setup to WR active
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wr.eq(1),
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NextState("WRITE0")
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)
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fsm.act("WRITE0",
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# 3.5ns D setup to WR inactive
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# 0ns D and A hold to WR inactive
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bus.ack.eq(1),
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NextState("IDLE")
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)
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fsm.act("READ",
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# 15ns D valid to A setup
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# 15ns D valid to RD active
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rx.eq(1),
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rd.eq(1),
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NextState("READ0")
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)
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fsm.act("READ0",
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rx.eq(1),
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rd.eq(1),
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NextState("READ1")
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)
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fsm.act("READ1",
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rx.eq(1),
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rd.eq(1),
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NextState("READ2")
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)
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fsm.act("READ2",
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rx.eq(1),
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rd.eq(1),
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NextState("READ3")
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)
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fsm.act("READ3",
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rx.eq(1),
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rd.eq(1),
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NextState("READ4")
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)
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fsm.act("READ4",
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rx.eq(1),
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NextState("READ5")
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)
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fsm.act("READ5",
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# 5ns D three-state to RD inactive
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# 10ns A hold to RD inactive
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rx.eq(1),
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bus.ack.eq(1),
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NextState("IDLE")
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)
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fsm.act("GPIO",
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bus.ack.eq(1),
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bus_r_gpio.eq(1),
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If(bus.we, gpio_load.eq(1)),
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NextState("IDLE")
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)
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fsm.act("FUD",
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# 4ns FUD setup to SYNCLK
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# 0ns FUD hold to SYNCLK
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fud.eq(1),
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bus.ack.eq(1),
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NextState("IDLE")
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)
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def _test_gen():
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# Test external bus writes
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yield TWrite(4, 2)
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yield TWrite(5, 3)
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yield
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# Test external bus reads
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yield TRead(14)
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yield TRead(15)
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yield
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# Test FUD
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yield TWrite(64, 0)
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yield
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# Test GPIO
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yield TWrite(65, 0xff)
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yield
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class _TestPads:
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def __init__(self):
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self.a = Signal(6)
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self.d = Signal(8)
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self.sel = Signal(5)
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self.p = Signal(2)
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self.fud_n = Signal()
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self.wr_n = Signal()
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self.rd_n = Signal()
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self.rst_n = Signal()
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class _TB(Module):
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def __init__(self):
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pads = _TestPads()
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self.submodules.dut = AD9858(pads)
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self.submodules.initiator = wishbone.Initiator(_test_gen())
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.initiator.bus, self.dut.bus)
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if __name__ == "__main__":
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run_simulation(_TB(), vcd_name="ad9858.vcd")
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