mirror of https://github.com/m-labs/artiq.git
111 lines
3.1 KiB
Python
111 lines
3.1 KiB
Python
"""RTIO driver for Mirny (4 channel GHz PLLs)
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"""
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from artiq.language.core import kernel, delay
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from artiq.language.units import us
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from numpy import int32
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (
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0 * spi.SPI_OFFLINE
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| 0 * spi.SPI_END
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| 0 * spi.SPI_INPUT
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| 1 * spi.SPI_CS_POLARITY
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| 0 * spi.SPI_CLK_POLARITY
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| 0 * spi.SPI_CLK_PHASE
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| 0 * spi.SPI_LSB_FIRST
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| 0 * spi.SPI_HALF_DUPLEX
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)
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# SPI clock write and read dividers
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SPIT_WR = 4
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SPIT_RD = 16
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SPI_CS = 1
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WE = 1 << 24
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class Mirny:
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"""
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Mirny PLL-based RF generator.
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:param spi_device: SPI bus device
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:param refclk: Reference clock (SMA, MMCX or on-board 100 MHz oscillator)
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frequency in Hz
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:param clk_sel: Reference clock selection.
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valid options are: 0 - internal 100MHz XO; 1 - front-panel SMA; 2 -
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internal MMCX
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:param core_device: Core device name (default: "core")
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"""
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kernel_invariants = {"bus", "core"}
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def __init__(self, dmgr, spi_device, refclk=100e6, clk_sel=0, core_device="core"):
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self.core = dmgr.get(core_device)
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self.bus = dmgr.get(spi_device)
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self.refclk = refclk
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assert 10 <= self.refclk / 1e6 <= 600, "Invalid refclk"
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self.clk_sel = clk_sel & 0b11
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assert 0 <= self.clk_sel <= 3, "Invalid clk_sel"
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# TODO: support clk_div on v1.0 boards
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@kernel
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def read_reg(self, addr):
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"""Read a register"""
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self.bus.set_config_mu(
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SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END, 24, SPIT_RD, SPI_CS
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)
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self.bus.write((addr << 25))
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return self.bus.read() & int32(0xFFFF)
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@kernel
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def write_reg(self, addr, data):
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"""Write a register"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 24, SPIT_WR, SPI_CS)
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self.bus.write((addr << 25) | WE | ((data & 0xFFFF) << 8))
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@kernel
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def init(self, blind=False):
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"""
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Initialize and detect Mirny.
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:param blind: Do not attempt to verify presence and compatibility.
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"""
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if not blind:
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reg0 = self.read_reg(0)
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if reg0 & 0b11 != 0b11:
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raise ValueError("Mirny HW_REV mismatch")
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if (reg0 >> 2) & 0b11 != 0b00:
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raise ValueError("Mirny PROTO_REV mismatch")
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delay(100 * us) # slack
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# select clock source
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self.write_reg(1, (self.clk_sel << 4))
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delay(1000 * us)
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@kernel
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def set_att_mu(self, channel, att):
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"""Set digital step attenuator in machine units.
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:param att: Attenuation setting, 8 bit digital.
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 16, SPIT_WR, SPI_CS)
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self.bus.write(((channel | 8) << 25) | (att << 16))
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@kernel
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def write_ext(self, addr, length, data):
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"""Perform SPI write to a prefixed address"""
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self.bus.set_config_mu(SPI_CONFIG, 8, SPIT_WR, SPI_CS)
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self.bus.write(addr << 25)
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, length, SPIT_WR, SPI_CS)
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if length < 32:
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data <<= 32 - length
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self.bus.write(data)
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