mirror of https://github.com/m-labs/artiq.git
104 lines
2.9 KiB
Python
104 lines
2.9 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg
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from artiq.gateware.rtio import rtlink
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class Output(Module):
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def __init__(self, pad):
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self.rtlink = rtlink.Interface(rtlink.OInterface(1))
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self.probes = [pad]
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override_en = Signal()
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override_o = Signal()
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self.overrides = [override_en, override_o]
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# # #
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pad_k = Signal()
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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pad_k.eq(self.rtlink.o.data)
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),
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If(override_en,
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pad.eq(override_o)
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).Else(
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pad.eq(pad_k)
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)
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]
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class Inout(Module):
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def __init__(self, pad):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(2, 2),
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rtlink.IInterface(1))
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override_en = Signal()
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override_o = Signal()
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override_oe = Signal()
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self.overrides = [override_en, override_o, override_oe]
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self.probes = []
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# # #
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ts = TSTriple()
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self.specials += ts.get_tristate(pad)
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sensitivity = Signal(2)
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o_k = Signal()
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oe_k = Signal()
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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If(self.rtlink.o.address == 0, o_k.eq(self.rtlink.o.data[0])),
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If(self.rtlink.o.address == 1, oe_k.eq(self.rtlink.o.data[0])),
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),
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If(override_en,
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ts.o.eq(override_o),
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ts.oe.eq(override_oe)
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).Else(
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ts.o.eq(o_k),
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ts.oe.eq(oe_k)
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)
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]
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self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
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sensitivity.eq(self.rtlink.o.data))
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i = Signal()
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i_d = Signal()
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self.specials += MultiReg(ts.i, i, "rio_phy")
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self.sync.rio_phy += i_d.eq(i)
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self.comb += [
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self.rtlink.i.stb.eq(
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(sensitivity[0] & ( i & ~i_d)) |
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(sensitivity[1] & (~i & i_d))
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),
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self.rtlink.i.data.eq(i)
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]
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self.probes += [i, ts.oe]
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class ClockGen(Module):
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def __init__(self, pad, ftw_width=24):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(ftw_width, suppress_nop=False))
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# # #
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ftw = Signal(ftw_width)
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acc = Signal(ftw_width)
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self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data))
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self.sync.rio_phy += [
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acc.eq(acc + ftw),
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# rtlink takes precedence over regular acc increments
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If(self.rtlink.o.stb,
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If(self.rtlink.o.data != 0,
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# known phase on frequency write: at rising edge
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acc.eq(2**(ftw_width - 1))
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).Else(
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# set output to 0 on stop
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acc.eq(0)
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)
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),
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pad.eq(acc[-1])
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]
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