mirror of https://github.com/m-labs/artiq.git
67 lines
2.4 KiB
Python
67 lines
2.4 KiB
Python
from migen import *
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from artiq.gateware import ad9xxx
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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class _AD9xxx(Module):
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def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
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self.submodules._ll = ClockDomainsRenamer("rio")(
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ad9xxx.AD9xxx(pads, **kwargs))
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self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
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self.rtlink = self._rt2wb.rtlink
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self.probes = [Signal(32) for i in range(nchannels)]
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# # #
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# buffer the current address/data on the rtlink output
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current_address = Signal.like(self.rtlink.o.address)
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current_data = Signal.like(self.rtlink.o.data)
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self.sync.rio += If(self.rtlink.o.stb,
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current_address.eq(self.rtlink.o.address),
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current_data.eq(self.rtlink.o.data))
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# keep track of the currently selected channel(s)
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current_sel = Signal(len(current_data)-1)
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self.sync.rio += If(current_address == 2**len(pads.a) + 1,
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current_sel.eq(current_data[1:])) # strip reset
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def selected(c):
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if onehot:
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return current_sel[c]
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else:
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return current_sel == c
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# keep track of frequency tuning words, before they are FUDed
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ftws = [Signal(32) for i in range(nchannels)]
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for c, ftw in enumerate(ftws):
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if len(pads.d) == 8:
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self.sync.rio_phy += \
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If(selected(c), [
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If(current_address == ftw_base+i,
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ftw[i*8:(i+1)*8].eq(current_data))
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for i in range(4)])
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elif len(pads.d) == 16:
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self.sync.rio_phy += \
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If(selected(c), [
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If(current_address == ftw_base+2*i,
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ftw[i*16:(i+1)*16].eq(current_data))
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for i in range(2)])
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else:
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raise NotImplementedError
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# FTW to probe on FUD
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self.sync.rio_phy += If(current_address == 2**len(pads.a), [
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If(selected(c), probe.eq(ftw))
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for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
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class AD9858(_AD9xxx):
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def __init__(self, *args, **kwargs):
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_AD9xxx.__init__(self, 0x0a, *args, **kwargs)
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class AD9914(_AD9xxx):
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def __init__(self, *args, **kwargs):
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_AD9xxx.__init__(self, 0x2d, *args, **kwargs)
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