mirror of https://github.com/m-labs/artiq.git
42 lines
1.4 KiB
YAML
42 lines
1.4 KiB
YAML
language: python
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python:
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- '3.4'
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env:
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global:
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- MSCDIR=$TRAVIS_BUILD_DIR/misoc
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- PATH=$HOME/miniconda/bin:/usr/local/llvm-or1k/bin:$PATH
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- CC=gcc-4.7
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- CXX=g++-4.7
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- ARTIQ_NO_HARDWARE=1
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- secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws="
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before_install:
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- ./.travis/get-toolchain.sh
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- ./.travis/get-xilinx.sh
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- ./.travis/get-anaconda.sh pip coverage numpy scipy sphinx
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- source $HOME/miniconda/bin/activate py34
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- sudo apt-get install --force-yes -y iverilog
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- pip install --src . -e 'git+https://github.com/m-labs/migen.git@master#egg=migen'
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- mkdir vpi
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- iverilog-vpi --name=vpi/migensim migen/vpi/main.c migen/vpi/ipc.c
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- git clone --recursive https://github.com/m-labs/misoc
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- pip install --src . -e 'git+https://github.com/nist-ionstorage/llvmlite.git@artiq#egg=llvmlite'
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- pip install coveralls
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install:
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- pip install -e .
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script:
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- coverage run --source=artiq setup.py test
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- make -C doc/manual html || true
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- cd misoc; python make.py -X ../soc -t artiq build-headers build-bios; cd ..
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- make -C soc/runtime
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- cd misoc; python make.py -X ../soc -t artiq build-bitstream; cd ..
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after_success:
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coveralls
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notifications:
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email: false
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irc:
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channels:
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- chat.freenode.net#m-labs
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webhooks:
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urls:
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- https://webhooks.gitter.im/e/d26782523952bfa53814
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