mirror of https://github.com/m-labs/artiq.git
72 lines
2.0 KiB
Python
72 lines
2.0 KiB
Python
import unittest
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import migen as mg
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from artiq.gateware.dsp.tools import SatAddMixin
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class DUT(mg.Module, SatAddMixin):
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def __init__(self, width):
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self.o = mg.Signal((width, True))
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self.i0 = mg.Signal.like(self.o)
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self.i1 = mg.Signal.like(self.o)
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self.l0 = mg.Signal.like(self.o)
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self.l1 = mg.Signal.like(self.o)
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self.c = mg.Signal(2)
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self.comb += self.o.eq(self.sat_add((self.i0, self.i1),
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width=4, limits=(self.l0, self.l1), clipped=self.c))
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class SatAddTest(unittest.TestCase):
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def setUp(self):
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self.dut = DUT(width=4)
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# import migen.fhdl.verilog
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# print(mg.fhdl.verilog.convert(self.dut))
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def _sweep(self):
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def gen():
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for i0 in range(-8, 8):
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yield self.dut.i0.eq(i0)
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for i1 in range(-8, 8):
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yield self.dut.i1.eq(i1)
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yield
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def rec():
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l0 = yield self.dut.l0
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l1 = yield self.dut.l1
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for i in range(1 << 8):
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i0 = yield self.dut.i0
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i1 = yield self.dut.i1
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o = yield self.dut.o
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c = yield self.dut.c
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full = i0 + i1
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lim = full
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clip = 0
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if full < l0:
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lim = l0
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clip = 1
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if full > l1:
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lim = l1
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clip = 2
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with self.subTest(i0=i0, i1=i1):
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self.assertEqual(lim, o)
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self.assertEqual(clip, c)
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yield
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mg.run_simulation(self.dut, (gen(), rec()))
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def test_inst(self):
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pass
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def test_run(self):
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self._sweep()
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def test_limits(self):
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for l0 in -8, 0, 1, 7:
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for l1 in -8, 0, 1, 7:
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self.setUp()
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self.dut.l0.reset = l0
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self.dut.l1.reset = l1
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with self.subTest(l0=l0, l1=l1):
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self._sweep()
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