mirror of https://github.com/m-labs/artiq.git
47 lines
1.3 KiB
Python
47 lines
1.3 KiB
Python
import logging
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from migen import *
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from artiq.coredevice.urukul import DEFAULT_PROFILE
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from . import spi
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logger = logging.getLogger(__name__)
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DDSParams = spi.SPIParams
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class DDS(spi.SPISimple):
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"""Multi-DDS SPI interface.
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* Supports SPI DDS chips like the AD9910.
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* Shifts data out to multiple DDS in parallel with a shared CLK and shared
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CS_N line.
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* Supports a single hardcoded command.
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* Configuration and setup must be done over a different channel.
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* Asserts IO_UPDATE for one clock cycle immediately after the SPI transfer.
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"""
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def __init__(self, pads, params):
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super().__init__(pads, params)
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self.profile = [Signal(32 + 16 + 16, reset_less=True)
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for i in range(params.channels)]
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# write to single tone default profile
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cmd = Signal(8, reset=0x0e + DEFAULT_PROFILE)
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assert params.width == len(cmd) + len(self.profile[0])
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self.sync += [
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If(self.start,
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[d.eq(Cat(p, cmd))
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for d, p in zip(self.data, self.profile)]
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)
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]
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# this assumes that the cycle time (1/125 MHz = 8 ns) is >1 SYNC_CLK
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# cycle (1/250 MHz = 4ns)
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done_old = Signal()
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self.sync += done_old.eq(self.done)
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self.comb += pads.io_update.eq(self.done & ~done_old)
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