mirror of https://github.com/m-labs/artiq.git
184 lines
6.7 KiB
Python
184 lines
6.7 KiB
Python
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import gpio, spi2
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from misoc.targets.efc import BaseSoC
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import eem_serdes
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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class Satellite(BaseSoC, AMPSoC):
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mem_map = {
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"rtio": 0x20000000,
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"drtioaux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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clk_freq=125e6,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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platform = self.platform
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drtio_eem_io = [
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("drtio_tx", 0,
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Subsignal("p", Pins("eem0:d0_cc_p eem0:d1_p eem0:d2_p eem0:d3_p")),
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Subsignal("n", Pins("eem0:d0_cc_n eem0:d1_n eem0:d2_n eem0:d3_n")),
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IOStandard("LVDS_25"),
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),
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("drtio_rx", 0,
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Subsignal("p", Pins("eem0:d4_p eem0:d5_p eem0:d6_p eem0:d7_p")),
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Subsignal("n", Pins("eem0:d4_n eem0:d5_n eem0:d6_n eem0:d7_n")),
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IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
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),
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]
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platform.add_extension(drtio_eem_io)
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data_pads = [
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(platform.request("drtio_rx"), platform.request("drtio_tx"))
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]
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# Disable SERVMOD, hardwire it to ground to enable EEM 0
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servmod = self.platform.request("servmod")
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self.comb += servmod.eq(0)
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self.submodules.eem_transceiver = eem_serdes.EEMSerdes(self.platform, data_pads)
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self.csr_devices.append("eem_transceiver")
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self.config["HAS_DRTIO_EEM"] = None
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self.config["EEM_TRANSCEIVERS"] = 1
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.eem_transceiver.channels[0],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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self.submodules.drtioaux0 = cdr(DRTIOAuxController(
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core.link_layer, self.cpu_dw))
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self.csr_devices.append("drtioaux0")
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memory_address = self.mem_map["drtioaux"]
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self.add_wb_slave(memory_address, 0x800, self.drtioaux0.bus)
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self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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i2c = self.platform.request("fpga_i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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# Enable I2C
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i2c_reset = self.platform.request("i2c_mux_rst_n")
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self.comb += i2c_reset.eq(1)
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fix_serdes_timing_path(platform)
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self.config["DRTIO_ROLE"] = "satellite"
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self.config["RTIO_FREQUENCY"] = "125.0"
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shuttler_io = [
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('dac_spi', 0,
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Subsignal('clk', Pins('fmc0:HB16_N')),
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Subsignal('mosi', Pins('fmc0:HB06_CC_N')),
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Subsignal('cs_n', Pins('fmc0:LA31_N fmc0:LA31_P fmc0:HB19_P fmc0:LA30_P')),
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IOStandard("LVCMOS18")),
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('dac_rst', 0, Pins('fmc0:HB16_P'), IOStandard("LVCMOS18")),
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]
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platform.add_extension(shuttler_io)
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(self.platform.request("dac_spi", 0)))
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self.csr_devices.append("converter_spi")
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self.config["HAS_CONVERTER_SPI"] = None
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dac_rst = self.platform.request('dac_rst')
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self.comb += dac_rst.eq(0)
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self.rtio_channels = []
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for i in range(2):
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phy = ttl_simple.Output(self.virtual_leds.get(i))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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def add_rtio(self, rtio_channels, sed_lanes=8):
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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# satellite (master-controlled) RTIO
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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# subkernel RTIO
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.register_kernel_cpu_csrdevice("rtio")
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri, self.rtio_dma.cri],
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[self.local_io.cri],
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enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.local_io.cri,
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self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
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self.csr_devices.append("rtio_analyzer")
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for EEM FMC Carrier systems")
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builder_args(parser)
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parser.set_defaults(output_dir="artiq_efc")
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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args = parser.parse_args()
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argdict = dict()
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argdict["gateware_identifier_str"] = args.gateware_identifier_str
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soc = Satellite(**argdict)
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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