mirror of https://github.com/m-labs/artiq.git
252 lines
8.4 KiB
Rust
252 lines
8.4 KiB
Rust
/*
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* HMC830 config:
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* 100MHz input, 1.2GHz output
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* fvco = (refclk / r_divider) * n_divider
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* fout = fvco/2
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*
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* HMC7043 config:
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* dac clock: 600MHz (div=2)
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* fpga clock: 150MHz (div=8)
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* sysref clock: 9.375MHz (div=128)
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*/
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mod clock_mux {
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use board::csr;
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const CLK_SRC_EXT_SEL : u8 = 1 << 0;
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const REF_CLK_SRC_SEL : u8 = 1 << 1;
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const DAC_CLK_SRC_SEL : u8 = 1 << 2;
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pub fn init() {
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unsafe {
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csr::clock_mux::out_write(
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1*CLK_SRC_EXT_SEL | // use ext clk from sma
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1*REF_CLK_SRC_SEL |
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1*DAC_CLK_SRC_SEL);
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}
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}
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}
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mod hmc830 {
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use board::{csr, clock};
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const HMC830_WRITES: [(u8, u32); 16] = [
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(0x0, 0x20),
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(0x1, 0x2),
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(0x2, 0x2), // r_divider
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(0x5, 0x1628),
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(0x5, 0x60a0),
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(0x5, 0xe110),
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(0x5, 0x2818),
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(0x5, 0x0),
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(0x6, 0x303ca),
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(0x7, 0x14d),
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(0x8, 0xc1beff),
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(0x9, 0x153fff),
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(0xa, 0x2046),
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(0xb, 0x7c061),
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(0xf, 0x81),
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(0x3, 0x30), // n_divider
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];
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fn spi_setup() {
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(0);
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csr::converter_spi::clk_div_write_write(8);
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csr::converter_spi::clk_div_read_write(8);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC830_CS);
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csr::converter_spi::offline_write(0);
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}
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}
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fn write(addr: u8, data: u32) {
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let cmd = (0 << 6) | addr;
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let val = ((cmd as u32) << 24) | data;
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unsafe {
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csr::converter_spi::xfer_len_write_write(32);
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csr::converter_spi::xfer_len_read_write(0);
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csr::converter_spi::data_write_write(val << (32-31));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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}
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}
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fn read(addr: u8) -> u32 {
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let cmd = (1 << 6) | addr;
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let val = (cmd as u32) << 24;
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unsafe {
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csr::converter_spi::xfer_len_write_write(7);
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csr::converter_spi::xfer_len_read_write(25);
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csr::converter_spi::data_write_write(val << (32-31));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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csr::converter_spi::data_read_read() & 0xffffff
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}
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}
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pub fn init() -> Result<(), &'static str> {
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spi_setup();
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let id = read(0x00);
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if id != 0xa7975 {
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error!("invalid HMC830 ID: 0x{:08x}", id);
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return Err("invalid HMC830 identification");
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} else {
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info!("HMC830 found");
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}
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info!("HMC830 configuration...");
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for &(addr, data) in HMC830_WRITES.iter() {
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write(addr, data);
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}
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let t = clock::get_ms();
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info!("waiting for lock...");
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while read(0x12) & 0x02 == 0 {
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if clock::get_ms() > t + 2000 {
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error!("HMC830 lock timeout. Register dump:");
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for addr in 0x00..0x14 {
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// These registers don't exist (in the data sheet at least)
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if addr == 0x0d || addr == 0x0e { continue; }
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error!("[0x{:02x}] = 0x{:04x}", addr, read(addr));
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}
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// return Err("HMC830 lock timeout");
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break;
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}
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}
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Ok(())
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}
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}
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mod hmc7043 {
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use board::csr;
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// To do: check which output channels we actually need
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const DAC_CLK_DIV: u32 = 2;
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const FPGA_CLK_DIV: u32 = 8;
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const SYSREF_DIV: u32 = 128;
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// enabled, divider, analog phase shift, digital phase shift
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const OUTPUT_CONFIG: [(bool, u32, u8, u8); 14] = [
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(true, DAC_CLK_DIV, 0x0, 0x0), // 0: DAC2_CLK
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(true, SYSREF_DIV, 0x0, 0x0), // 1: DAC2_SYSREF
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(true, DAC_CLK_DIV, 0x0, 0x0), // 2: DAC1_CLK
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(true, SYSREF_DIV, 0x0, 0x0), // 3: DAC1_SYSREF
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(false, 0, 0x0, 0x0), // 4: ADC2_CLK
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(false, 0, 0x0, 0x0), // 5: ADC2_SYSREF
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(true, FPGA_CLK_DIV, 0x0, 0x0), // 6: GTP_CLK2
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(true, SYSREF_DIV, 0x0, 0x0), // 7: FPGA_DAC_SYSREF
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(true, FPGA_CLK_DIV, 0x0, 0x0), // 8: GTP_CLK1
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(true, FPGA_CLK_DIV, 0x0, 0x0), // 9: AMC_MASTER_AUX_CLK
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(true, FPGA_CLK_DIV, 0x0, 0x0), // 10: RTM_MASTER_AUX_CLK
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(false, 0, 0x0, 0x0), // 11: FPGA_ADC_SYSREF
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(false, 0, 0x0, 0x0), // 12: ADC1_CLK
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(false, 0, 0x0, 0x0), // 13: ADC1_SYSREF
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];
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fn spi_setup() {
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(1);
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csr::converter_spi::clk_div_write_write(8);
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csr::converter_spi::clk_div_read_write(8);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC7043_CS);
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csr::converter_spi::offline_write(0);
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}
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}
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fn write(addr: u16, data: u8) {
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let cmd = (0 << 15) | addr;
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let val = ((cmd as u32) << 8) | data as u32;
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unsafe {
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csr::converter_spi::xfer_len_write_write(24);
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csr::converter_spi::xfer_len_read_write(0);
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csr::converter_spi::data_write_write(val << (32-24));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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}
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}
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fn read(addr: u16) -> u8 {
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let cmd = (1 << 15) | addr;
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let val = (cmd as u32) << 8;
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unsafe {
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csr::converter_spi::xfer_len_write_write(16);
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csr::converter_spi::xfer_len_read_write(8);
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csr::converter_spi::data_write_write(val << (32-24));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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csr::converter_spi::data_read_read() as u8
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}
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}
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pub fn init() -> Result<(), &'static str> {
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spi_setup();
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let id = (read(0x78) as u32) << 16 | (read(0x79) as u32) << 8 | read(0x7a) as u32;
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if id != 0xf17904 {
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error!("invalid HMC7043 ID: 0x{:08x}", id);
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return Err("invalid HMC7043 identification");
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} else {
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info!("HMC7043 found");
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}
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info!("HMC7043 configuration...");
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write(0x0, 0x1); // Software reset
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write(0x0, 0x0);
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write(0x1, 0x40); // Enable high-performace/low-noise mode
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write(0x3, 0x10); // Disable SYSREF timer
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write(0xA, 0x06); // Disable the REFSYNCIN input
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write(0xB, 0x07); // Enable the CLKIN input as LVPECL
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write(0x50, 0x1f); // Disable GPO pin
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write(0x9F, 0x4d); // Unexplained high-performance mode
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write(0xA0, 0xdf); // Unexplained high-performance mode
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// Enable required output groups
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write(0x4, (1 << 0) |
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(1 << 1) |
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(1 << 3) |
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(1 << 4) |
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(1 << 5));
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for channel in 0..14 {
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let channel_base = 0xc8 + 0x0a*(channel as u16);
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let (enabled, divider, aphase, dphase) = OUTPUT_CONFIG[channel];
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if enabled {
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// Only clock channels need to be high-performance
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if (channel % 2) == 0 { write(channel_base, 0x91); }
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else { write(channel_base, 0x11); }
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}
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else { write(channel_base, 0x10); }
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write(channel_base + 0x1, (divider & 0x0ff) as u8);
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write(channel_base + 0x2, ((divider & 0x700) >> 8) as u8);
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write(channel_base + 0x3, aphase & 0x1f);
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write(channel_base + 0x4, dphase & 0x1f);
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// No analog phase shift on clock channels
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if (channel % 2) == 0 { write(channel_base + 0x7, 0x00); }
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else { write(channel_base + 0x7, 0x01); }
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write(channel_base + 0x8, 0x08)
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}
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Ok(())
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}
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}
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pub fn init() -> Result<(), &'static str> {
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clock_mux::init();
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hmc830::init()?;
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hmc7043::init()
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}
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