mirror of https://github.com/m-labs/artiq
217 lines
6.2 KiB
Rust
217 lines
6.2 KiB
Rust
use core::result;
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use i2c;
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use clock;
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use csr;
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type Result<T> = result::Result<T, &'static str>;
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const BUSNO: u8 = 0;
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const ADDRESS: u8 = 0x68;
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#[cfg(any(soc_platform = "sayma_amc", soc_platform = "kc705"))]
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fn pca9548_select(address: u8, channel: u8) -> Result<()> {
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i2c::start(BUSNO).unwrap();
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if !i2c::write(BUSNO, (address << 1)).unwrap() {
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return Err("PCA9548 failed to ack write address")
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}
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if !i2c::write(BUSNO, 1 << channel).unwrap() {
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return Err("PCA9548 failed to ack control word")
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}
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i2c::stop(BUSNO).unwrap();
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Ok(())
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}
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fn reset(en: bool) {
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unsafe {
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csr::si5324_rst_n::out_write(if en { 0 } else { 1 })
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}
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}
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// NOTE: the logical parameters DO NOT MAP to physical values written
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// into registers. They have to be mapped; see the datasheet.
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// DSPLLsim reports the logical parameters in the design summary, not
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// the physical register values.
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pub struct FrequencySettings {
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pub n1_hs: u8,
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pub nc1_ls: u32,
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pub n2_hs: u8,
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pub n2_ls: u32,
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pub n31: u32,
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pub n32: u32,
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pub bwsel: u8
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}
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fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySettings> {
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if settings.nc1_ls != 0 && (settings.nc1_ls % 2) == 1 {
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return Err("NC1_LS must be 0 or even")
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}
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if settings.nc1_ls > (1 << 20) {
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return Err("NC1_LS is too high")
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}
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if (settings.n2_ls % 2) == 1 {
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return Err("N2_LS must be even")
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}
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if settings.n2_ls > (1 << 20) {
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return Err("N2_LS is too high")
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}
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if settings.n31 > (1 << 19) {
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return Err("N31 is too high")
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}
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if settings.n32 > (1 << 19) {
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return Err("N32 is too high")
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}
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let r = FrequencySettings {
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n1_hs: match settings.n1_hs {
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4 => 0b000,
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5 => 0b001,
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6 => 0b010,
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7 => 0b011,
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8 => 0b100,
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("N1_HS has an invalid value")
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},
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nc1_ls: settings.nc1_ls - 1,
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n2_hs: match settings.n2_hs {
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4 => 0b000,
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5 => 0b001,
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6 => 0b010,
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7 => 0b011,
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8 => 0b100,
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("N2_HS has an invalid value")
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},
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n2_ls: settings.n2_ls - 1,
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n31: settings.n31 - 1,
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n32: settings.n32 - 1,
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bwsel: settings.bwsel
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};
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Ok(r)
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}
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fn write(reg: u8, val: u8) -> Result<()> {
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i2c::start(BUSNO).unwrap();
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if !i2c::write(BUSNO, (ADDRESS << 1)).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c::write(BUSNO, reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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if !i2c::write(BUSNO, val).unwrap() {
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return Err("Si5324 failed to ack value")
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}
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i2c::stop(BUSNO).unwrap();
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Ok(())
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}
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fn read(reg: u8) -> Result<u8> {
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i2c::start(BUSNO).unwrap();
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if !i2c::write(BUSNO, (ADDRESS << 1)).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c::write(BUSNO, reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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i2c::restart(BUSNO).unwrap();
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if !i2c::write(BUSNO, (ADDRESS << 1) | 1).unwrap() {
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return Err("Si5324 failed to ack read address")
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}
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let val = i2c::read(BUSNO, false).unwrap();
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i2c::stop(BUSNO).unwrap();
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Ok(val)
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}
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fn ident() -> Result<u16> {
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Ok(((read(134)? as u16) << 8) | (read(135)? as u16))
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}
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fn has_xtal() -> Result<bool> {
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Ok((read(129)? & 0x01) == 0) // LOSX_INT=0
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}
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fn has_clkin2() -> Result<bool> {
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Ok((read(129)? & 0x04) == 0) // LOS2_INT=0
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}
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fn locked() -> Result<bool> {
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Ok((read(130)? & 0x01) == 0) // LOL_INT=0
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}
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fn monitor_lock() -> Result<()> {
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let t = clock::get_ms();
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while !locked()? {
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// Yes, lock can be really slow.
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if clock::get_ms() > t + 20000 {
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return Err("Si5324 lock timeout");
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}
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}
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info!("Si5324 is locked");
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Ok(())
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}
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pub fn setup(settings: &FrequencySettings) -> Result<()> {
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let s = map_frequency_settings(settings)?;
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reset(true);
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clock::spin_us(1_000);
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reset(false);
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clock::spin_us(10_000);
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#[cfg(soc_platform = "kc705")]
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pca9548_select(0x74, 7)?;
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#[cfg(soc_platform = "sayma_amc")]
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pca9548_select(0x70, 4)?;
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if ident()? != 0x0182 {
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return Err("Si5324 does not have expected product number");
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}
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write(0, read(0)? | 0x40)?; // FREE_RUN=1
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write(2, (read(2)? & 0x0f) | (s.bwsel << 4))?;
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write(21, read(21)? & 0xfe)?; // CKSEL_PIN=0
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write(3, (read(3)? & 0x3f) | (0b01 << 6) | 0x10)?; // CKSEL_REG=b01 SQ_ICAL=1
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write(4, (read(4)? & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
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write(6, (read(6)? & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
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write(25, (s.n1_hs << 5 ) as u8)?;
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write(31, (s.nc1_ls >> 16) as u8)?;
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write(32, (s.nc1_ls >> 8 ) as u8)?;
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write(33, (s.nc1_ls) as u8)?;
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write(34, (s.nc1_ls >> 16) as u8)?; // write to NC2_LS as well
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write(35, (s.nc1_ls >> 8 ) as u8)?;
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write(36, (s.nc1_ls) as u8)?;
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write(40, (s.n2_hs << 5 ) as u8 | (s.n2_ls >> 16) as u8)?;
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write(41, (s.n2_ls >> 8 ) as u8)?;
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write(42, (s.n2_ls) as u8)?;
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write(43, (s.n31 >> 16) as u8)?;
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write(44, (s.n31 >> 8) as u8)?;
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write(45, (s.n31) as u8)?;
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write(46, (s.n32 >> 16) as u8)?;
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write(47, (s.n32 >> 8) as u8)?;
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write(48, (s.n32) as u8)?;
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write(137, read(137)? | 0x01)?; // FASTLOCK=1
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write(136, read(136)? | 0x40)?; // ICAL=1
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if !has_xtal()? {
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return Err("Si5324 misses XA/XB signal");
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}
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if !has_clkin2()? {
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return Err("Si5324 misses CLKIN2 signal");
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}
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monitor_lock()?;
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Ok(())
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}
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pub fn select_ext_input(external: bool) -> Result<()> {
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if external {
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write(3, (read(3)? & 0x3f) | (0b00 << 6))?; // CKSEL_REG=b00
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} else {
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write(3, (read(3)? & 0x3f) | (0b01 << 6))?; // CKSEL_REG=b01
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}
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monitor_lock()?;
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Ok(())
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}
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