mirror of https://github.com/m-labs/artiq
46 lines
1.1 KiB
Rust
46 lines
1.1 KiB
Rust
use core::ptr;
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use super::spr::*;
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use csr;
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use mem;
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pub fn flush_cpu_icache() {
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unsafe {
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let iccfgr = mfspr(SPR_ICCFGR);
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let ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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let set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
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let block_size = if iccfgr & SPR_ICCFGR_CBS != 0 { 32 } else { 16 };
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let size = set_size * ways * block_size;
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let mut i = 0;
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while i < size {
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mtspr(SPR_ICBIR, i);
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i += block_size;
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}
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}
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}
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pub fn flush_cpu_dcache() {
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unsafe {
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let dccfgr = mfspr(SPR_DCCFGR);
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let ways = 1 << (dccfgr & SPR_ICCFGR_NCW);
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let set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
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let block_size = if dccfgr & SPR_DCCFGR_CBS != 0 { 32 } else { 16 };
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let size = set_size * ways * block_size;
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let mut i = 0;
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while i < size {
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mtspr(SPR_DCBIR, i);
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i += block_size;
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}
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}
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}
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pub fn flush_l2_cache() {
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unsafe {
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for i in 0..2 * (csr::CONFIG_L2_SIZE as usize) / 4 {
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let addr = mem::MAIN_RAM_BASE + i * 4;
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ptr::read_volatile(addr as *const usize);
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}
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}
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}
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