mirror of https://github.com/m-labs/artiq
68 lines
2.3 KiB
Python
Executable File
68 lines
2.3 KiB
Python
Executable File
#!/usr/bin/env python3.5
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# Copyright 2014-2017 Robert Jordens <jordens@gmail.com>
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# after
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# https://github.com/mfischer/fpgadev-zynq/blob/master/top/python/bit_to_zynq_bin.py
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import struct
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def flip32(data):
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sl = struct.Struct("<I")
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sb = struct.Struct(">I")
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b = memoryview(data)
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d = bytearray(len(data))
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for offset in range(0, len(data), sl.size):
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sb.pack_into(d, offset, *sl.unpack_from(b, offset))
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return d
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def bit2bin(bit, bin, flip=False):
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with open(bit, "rb") as bitfile:
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l, = struct.unpack(">H", bitfile.read(2))
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if l != 9:
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raise ValueError("Missing <0009> header, not a bit file")
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bitfile.read(l)
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d = bitfile.read(*struct.unpack(">H", bitfile.read(2)))
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if d != b"a":
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raise ValueError("Missing <a> header, not a bit file")
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d = bitfile.read(*struct.unpack(">H", bitfile.read(2)))
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print("Design name:", d)
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while True:
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key = bitfile.read(1)
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if not key:
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break
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if key in b"bcd":
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d = bitfile.read(*struct.unpack(">H", bitfile.read(2)))
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name = {b"b": "Partname", b"c": "Date", b"d": "Time"}[key]
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print(name, d)
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elif key == b"e":
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l, = struct.unpack(">I", bitfile.read(4))
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print("found binary data length:", l)
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d = bitfile.read(l)
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if flip:
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d = flip32(d)
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with open(bin, "wb") as f:
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f.write(d)
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else:
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d = bitfile.read(*struct.unpack(">H", bitfile.read(2)))
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print("Unexpected key: ", key, d)
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if __name__ == "__main__":
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import argparse
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parser = argparse.ArgumentParser(
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description="Convert FPGA bit files to raw bin format "
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"suitable for flashing")
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parser.add_argument("-f", "--flip", dest="flip", action="store_true",
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default=False, help="Flip 32-bit endianess (needed for Zynq)")
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parser.add_argument("bitfile", metavar="BITFILE",
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help="Input bit file name")
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parser.add_argument("binfile", metavar="BINFILE",
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help="Output bin file name")
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args = parser.parse_args()
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bit2bin(args.bitfile, args.binfile, args.flip)
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