artiq/artiq/examples
Robert Jördens f4dd7e5e29 kasli_tester: init urukul channel before calibrating
Otherwise the DDS is not initialized and with a cold system it fails to
find IO_UPDATE edges.

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-09-11 07:16:35 +00:00
..
kasli kasli_tester: init urukul channel before calibrating 2019-09-11 07:16:35 +00:00
kasli_drtioswitching kasli: cleanup drtio blink example 2018-09-15 18:43:27 +08:00
kasli_sawgmaster kasli_sawgmaster: generate a HMC830 clock with Urukul 2019-01-29 15:06:45 +08:00
kasli_suservo suservo: extract boilerplate 2018-06-01 15:37:07 +00:00
kc705_nist_clock examples/dds_setter: fix RTIO underflow 2019-06-13 18:07:39 +08:00
no_hardware ttl: Add target RTIO time argument to timestamp/count functions 2018-11-03 20:33:19 +08:00
sayma_master sayma: update fmcdio_vhdci_eem demo 2018-07-19 15:47:20 +08:00
sayma_standalone examples: change Sayma sines frequency to 9MHz 2018-06-20 22:40:07 +08:00
artiq_ipython_notebook.ipynb generate device database from executable python file 2017-05-18 23:14:55 +08:00
fit_image.py ship examples with package 2016-04-05 13:59:39 +08:00
remote_exec_controller.py python3.5 -> python3 2017-01-30 09:24:43 +08:00