Robert Jördens 8f54a1e619 pipistrello: sys_clk 83 -> 75 MHz ... This should close #341 once migen generates stable output.		2016-03-21 13:47:32 +01:00
..
amp	Implement core device storage (fixes #219).	2016-01-10 13:04:55 +00:00
rtio	analyzer: make byte_count 64-bit	2016-03-19 19:40:23 +08:00
targets	pipistrello: sys_clk 83 -> 75 MHz	2016-03-21 13:47:32 +01:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9xxx.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_clock.py	gateware/nist_{clock,qc2}: do not conflict with KC705 I2C	2016-03-03 15:10:50 +08:00
nist_qc1.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_qc2.py	targets/kc705/qc2: hook up HPC backplane	2016-03-16 16:19:56 +08:00
soc.py	soc: use add_extra_software_packages, factor builder code	2016-03-07 00:18:47 +08:00
spi.py	gateware.spi: delay only writes to data register, update doc	2016-03-01 14:14:38 +01:00