mirror of https://github.com/m-labs/artiq.git
98 lines
3.5 KiB
Python
98 lines
3.5 KiB
Python
from artiq.language.core import (kernel, seconds_to_mu, now_mu,
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delay_mu, int)
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from artiq.language.units import MHz
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from artiq.coredevice.rtio import rtio_output as rt2wb_output
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from artiq.coredevice.rt2wb import rt2wb_input
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SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
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(
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SPI_OFFLINE,
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SPI_ACTIVE,
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SPI_PENDING,
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SPI_CS_POLARITY,
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SPI_CLK_POLARITY,
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SPI_CLK_PHASE,
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SPI_LSB_FIRST,
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SPI_HALF_DUPLEX,
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) = (1 << i for i in range(8))
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SPI_RT2WB_READ = 1 << 2
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class SPIMaster:
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"""Core device Serial Peripheral Interface (SPI) bus master.
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:param ref_period: clock period of the SPI core.
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:param channel: channel number of the SPI bus to control.
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"""
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def __init__(self, dmgr, ref_period, channel):
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self.core = dmgr.get("core")
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self.ref_period = ref_period
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self.ref_period_mu = int(seconds_to_mu(ref_period, self.core))
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self.channel = channel
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self.write_period_mu = int(0)
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self.read_period_mu = int(0)
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self.xfer_period_mu = int(0)
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# A full transfer takes write_period_mu + xfer_period_mu.
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# Chained transfers can happen every xfer_period_mu.
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# The second transfer of a chain can be written 2*ref_period_mu
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# after the first. Read data is available every xfer_period_mu starting
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# a bit after xfer_period_mu (depending on clk_phase).
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# To chain transfers together, new data must be written before
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# pending transfer's read data becomes available.
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@kernel
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def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
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write_div = round(1/(write_freq*self.ref_period))
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read_div = round(1/(read_freq*self.ref_period))
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self.set_config_mu(flags, write_div, read_div)
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@kernel
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def set_config_mu(self, flags=0, write_div=6, read_div=6):
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rt2wb_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
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((write_div - 2) << 16) | ((read_div - 2) << 24))
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self.write_period_mu = int(write_div*self.ref_period_mu)
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self.read_period_mu = int(read_div*self.ref_period_mu)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def set_xfer(self, chip_select=0, write_length=0, read_length=0):
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rt2wb_output(now_mu(), self.channel, SPI_XFER_ADDR,
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chip_select | (write_length << 16) | (read_length << 24))
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self.xfer_period_mu = int(write_length*self.write_period_mu +
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read_length*self.read_period_mu)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def write(self, data):
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rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def read_async(self):
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# every read_async() must be matched by an input_async()
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rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def input_async(self):
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# matches the preeeding read_async()
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return rt2wb_input(self.channel)
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@kernel
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def read_sync(self):
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rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
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return rt2wb_input(self.channel)
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@kernel
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def _get_xfer_sync(self):
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rt2wb_output(now_mu(), self.channel, SPI_XFER_ADDR | SPI_RT2WB_READ, 0)
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return rt2wb_input(self.channel)
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@kernel
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def _get_config_sync(self):
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rt2wb_output(now_mu(), self.channel, SPI_CONFIG_ADDR | SPI_RT2WB_READ,
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0)
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return rt2wb_input(self.channel)
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