mirror of https://github.com/m-labs/artiq.git
85 lines
2.7 KiB
Python
85 lines
2.7 KiB
Python
import unittest
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from migen import *
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from artiq.gateware.rtio.phy.fastlink import *
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class TestPhaser(unittest.TestCase):
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def setUp(self):
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self.dut = SerDes(n_data=8, t_clk=8, d_clk=0b00001111,
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n_frame=10, n_crc=6, poly=0x2f)
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def test_init(self):
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pass
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def record_frame(self, frame):
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clk = 0
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marker = 0
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stb = 0
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while True:
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if stb == 2:
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frame.append((yield self.dut.data))
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clk = (clk << 2) & 0xff
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clk |= (yield self.dut.data[0])
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if clk == 0x0f:
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if marker == 0x01:
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stb += 1
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if stb >= 3:
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break
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# 10/2 + 1 marker bits
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marker = (marker << 1) & 0x3f
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marker |= (yield self.dut.data[1]) & 1
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yield
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def test_frame(self):
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frame = []
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self.dut.comb += self.dut.payload.eq((1 << len(self.dut.payload)) - 1)
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run_simulation(self.dut, self.record_frame(frame),
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clocks={n: 2 for n in ["sys", "rio", "rio_phy"]})
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self.assertEqual(len(frame), 8*10//2)
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self.assertEqual([d[0] for d in frame], [0, 0, 3, 3] * 10)
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self.assertEqual([d[1] & 1 for d in frame[4*4 - 1:10*4 - 1:4]],
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[0, 0, 0, 0, 0, 1])
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class TestFastino(unittest.TestCase):
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def setUp(self):
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self.dut = SerDes(
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n_data=8, t_clk=7, d_clk=0b1100011,
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n_frame=14, n_crc=12, poly=0x80f)
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def test_init(self):
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pass
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def record_frame(self, frame):
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clk = 0
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marker = 0
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stb = 0
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while True:
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if stb == 2:
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frame.append((yield self.dut.data))
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clk = (clk << 2) & 0xff
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clk |= (yield self.dut.data[0])
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if clk in (0b11100011, 0b11000111):
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if marker == 0x01:
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stb += 1
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if stb >= 3:
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break
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# 14/2 + 1 marker bits
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marker = (marker << 1) & 0xff
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if clk & 0b100:
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marker |= (yield self.dut.data[1]) >> 1
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else:
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marker |= (yield self.dut.data[1]) & 1
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yield
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def test_frame(self):
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frame = []
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self.dut.comb += self.dut.payload.eq((1 << len(self.dut.payload)) - 1)
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run_simulation(self.dut, self.record_frame(frame),
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clocks={n: 2 for n in ["sys", "rio", "rio_phy"]})
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self.assertEqual(len(frame), 7*14//2)
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self.assertEqual([d[0] for d in frame], [3, 0, 1, 3, 2, 0, 3] * 7)
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self.assertEqual(frame[-1], [3, 3, 1, 1, 1, 2, 1, 0]) # crc12
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