mirror of https://github.com/m-labs/artiq.git
133 lines
4.2 KiB
Python
133 lines
4.2 KiB
Python
import logging
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import string
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from collections import namedtuple
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from migen import *
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from migen.genlib import io
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logger = logging.getLogger(__name__)
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# all times in cycles
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ADCParams = namedtuple("ADCParams", [
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"channels", # number of channels
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"lanes", # number of SDO? data lanes
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# lanes need to be named alphabetically and contiguous
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# (e.g. [sdoa, sdob, sdoc, sdoc] or [sdoa, sdob])
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"width", # bits to transfer per channel
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"t_cnvh", # CNVH duration (minimum)
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"t_conv", # CONV duration (minimum)
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"t_rtt", # upper estimate for clock round trip time from
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# sck at the FPGA to clkout at the FPGA (cycles)
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# this avoids having synchronizers and another counter
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# to signal end-of transfer
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# and it ensures fixed latency early in the pipeline
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])
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class ADC(Module):
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"""Multi-lane, multi-channel, triggered, source-synchronous, serial
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ADC interface.
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* Supports ADCs like the LTC2320-16.
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* Hardcoded timings.
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"""
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def __init__(self, pads, params):
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self.params = p = params # ADCParams
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self.data = [Signal((p.width, True), reset_less=True)
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for i in range(p.channels)] # retrieved ADC data
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self.start = Signal() # start conversion and reading
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self.reading = Signal() # data is being read (outputs are invalid)
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self.done = Signal() # data is valid and a new conversion can
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# be started
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###
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# collect sdo lines
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sdo = []
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for i in string.ascii_lowercase[:p.lanes]:
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sdo.append(getattr(pads, "sdo" + i))
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assert p.lanes == len(sdo)
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# set up counters for the four states CNVH, CONV, READ, RTT
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t_read = p.width*p.channels//p.lanes # SDR
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assert p.lanes*t_read == p.width*p.channels
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assert all(_ > 0 for _ in (p.t_cnvh, p.t_conv, p.t_rtt))
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assert p.t_conv > 1
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count = Signal(max=max(p.t_cnvh, p.t_conv, t_read, p.t_rtt),
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reset_less=True)
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count_load = Signal.like(count)
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count_done = Signal()
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update = Signal()
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self.comb += count_done.eq(count == 0)
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self.sync += [
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count.eq(count - 1),
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If(count_done,
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count.eq(count_load),
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)
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]
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self.submodules.fsm = fsm = FSM("IDLE")
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fsm.act("IDLE",
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self.done.eq(1),
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If(self.start,
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count_load.eq(p.t_cnvh - 1),
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NextState("CNVH")
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)
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)
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fsm.act("CNVH",
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count_load.eq(p.t_conv - 1),
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pads.cnv.eq(1),
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If(count_done,
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NextState("CONV")
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)
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)
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fsm.act("CONV",
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count_load.eq(t_read - 1),
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If(count_done,
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NextState("READ")
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)
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)
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fsm.act("READ",
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self.reading.eq(1),
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count_load.eq(p.t_rtt - 1),
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pads.sck_en.eq(1),
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If(count_done,
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NextState("RTT")
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)
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)
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fsm.act("RTT", # account for sck->clkout round trip time
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self.reading.eq(1),
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If(count_done,
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update.eq(1),
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NextState("IDLE")
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)
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)
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try:
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sck_en_ret = pads.sck_en_ret # simulation
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except AttributeError:
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sck_en_ret = 1
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self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
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self.comb += self.cd_ret.clk.eq(pads.clkout)
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k = p.channels//p.lanes
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assert t_read == k*p.width
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for i, sdo in enumerate(sdo):
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sdo_sr = Signal(2*t_read)
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self.sync.ret += [
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If(sck_en_ret,
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sdo_sr[1:].eq(sdo_sr),
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sdo_sr[0].eq(sdo),
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)
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]
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self.sync += [
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If(update,
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Cat(reversed([self.data[i*k + j] for j in range(k)])
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).eq(sdo_sr)
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)
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]
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