mirror of https://github.com/m-labs/artiq.git
22 lines
687 B
Python
22 lines
687 B
Python
from migen import *
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from misoc.interconnect import wishbone
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class Mailbox(Module):
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def __init__(self, size=1, adr_width=30):
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self.i1 = wishbone.Interface(data_width=32, adr_width=adr_width)
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self.i2 = wishbone.Interface(data_width=32, adr_width=adr_width)
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# # #
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values = Array([Signal(32) for _ in range(size)])
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for i in self.i1, self.i2:
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self.sync += [
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i.dat_r.eq(values[i.adr[:bits_for(size-1)]]),
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i.ack.eq(0),
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If(i.cyc & i.stb & ~i.ack,
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i.ack.eq(1),
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If(i.we, values[i.adr[:bits_for(size-1)]].eq(i.dat_w))
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)
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]
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