mirror of https://github.com/m-labs/artiq.git
68 lines
1.5 KiB
C
68 lines
1.5 KiB
C
#include <stdio.h>
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#include <generated/csr.h>
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#include "clock.h"
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#include "flash_storage.h"
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#include "rtiocrg.h"
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void rtiocrg_init(void)
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{
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char b;
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int clk;
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(0);
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#endif
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b = 'i';
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clk = 0;
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fs_read("startup_clock", &b, 1, NULL);
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if(b == 'i')
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printf("Startup RTIO clock: internal\n");
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else if(b == 'e') {
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printf("Startup RTIO clock: external\n");
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clk = 1;
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} else
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printf("WARNING: unknown startup_clock entry in flash storage\n");
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if(!rtiocrg_switch_clock(clk)) {
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printf("WARNING: startup RTIO clock failed\n");
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printf("WARNING: this may cause the system initialization to fail\n");
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printf("WARNING: fix clocking and reset the device\n");
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}
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}
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int rtiocrg_check(void)
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{
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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return rtio_crg_pll_locked_read();
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#else
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return 1;
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#endif
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}
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int rtiocrg_switch_clock(int clk)
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{
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int current_clk;
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current_clk = rtio_crg_clock_sel_read();
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if(clk == current_clk) {
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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busywait_us(150);
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if(!rtio_crg_pll_locked_read())
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return 0;
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#endif
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return 1;
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}
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(1);
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#endif
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rtio_crg_clock_sel_write(clk);
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(0);
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busywait_us(150);
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if(!rtio_crg_pll_locked_read())
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return 0;
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#endif
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return 1;
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}
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