mirror of https://github.com/m-labs/artiq.git
440 lines
16 KiB
Python
440 lines
16 KiB
Python
from functools import reduce
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from operator import and_
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from migen import *
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from migen.genlib.record import Record
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import cri, rtlink
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from artiq.gateware.rtio.cdc import *
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# CHOOSING A GUARD TIME
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#
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# The buffer must be transferred to the FIFO soon enough to account for:
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# * transfer of counter to sys domain: Tio + 2*Tsys + Tsys
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# * FIFO latency: Tsys + 2*Tio
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# * FIFO buffer latency: Tio
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# Therefore we must choose:
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# guard_io_cycles > (4*Tio + 4*Tsys)/Tio
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#
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# We are writing to the FIFO from the buffer when the guard time has been
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# reached. This can fill the FIFO and deassert the writable flag. A race
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# condition occurs that causes problems if the deassertion happens between
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# the CPU checking the writable flag (and reading 1) and writing a new event.
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#
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# When the FIFO is about to be full, it contains fifo_depth-1 events of
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# strictly increasing timestamps.
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#
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# Thus the FIFO-filling event's timestamp must satisfy:
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# timestamp*Tio > (fifo_depth-1)*Tio + time
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# We also have (guard time reached):
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# timestamp*Tio < time + guard_io_cycles*Tio
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# [NB: time > counter.value_sys*Tio]
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# Thus we must have:
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# guard_io_cycles > fifo_depth-1
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#
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# We can prevent overflows by choosing instead:
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# guard_io_cycles < fifo_depth-1
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class _OutputManager(Module):
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def __init__(self, interface, counter, fifo_depth, guard_io_cycles):
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data_width = rtlink.get_data_width(interface)
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address_width = rtlink.get_address_width(interface)
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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ev_layout = []
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if data_width:
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ev_layout.append(("data", data_width))
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if address_width:
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ev_layout.append(("address", address_width))
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ev_layout.append(("timestamp", counter.width + fine_ts_width))
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# ev must be valid 1 cycle before we to account for the latency in
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# generating replace, sequence_error and collision
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self.ev = Record(ev_layout)
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self.writable = Signal()
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self.we = Signal() # maximum throughput 1/2
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self.underflow = Signal() # valid 1 cycle after we, pulsed
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self.sequence_error = Signal()
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self.collision = Signal()
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self.busy = Signal() # pulsed
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# # #
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# FIFO
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fifo = ClockDomainsRenamer({"write": "rsys", "read": "rio"})(
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AsyncFIFO(layout_len(ev_layout), fifo_depth))
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self.submodules += fifo
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fifo_in = Record(ev_layout)
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fifo_out = Record(ev_layout)
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self.comb += [
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout)
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]
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# Buffer
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buf_pending = Signal()
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buf = Record(ev_layout)
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buf_just_written = Signal()
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# Special cases
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replace = Signal()
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sequence_error = Signal()
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collision = Signal()
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any_error = Signal()
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if interface.enable_replace:
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# Note: replace may be asserted at the same time as collision
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# when addresses are different. In that case, it is a collision.
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self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
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buf.timestamp[fine_ts_width:])
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if interface.enable_replace:
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if address_width:
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different_addresses = self.ev.address != buf.address
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else:
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different_addresses = 0
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if fine_ts_width:
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self.sync.rsys += collision.eq(
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(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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& ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
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|different_addresses))
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else:
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self.sync.rsys += collision.eq(
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self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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self.comb += [
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any_error.eq(sequence_error | collision),
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self.sequence_error.eq(self.we & sequence_error),
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self.collision.eq(self.we & collision)
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]
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# Buffer read and FIFO write
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self.comb += fifo_in.eq(buf)
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in_guard_time = Signal()
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self.comb += in_guard_time.eq(
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buf.timestamp[fine_ts_width:]
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< counter.value_sys + guard_io_cycles)
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self.sync.rsys += If(in_guard_time, buf_pending.eq(0))
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self.comb += \
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If(buf_pending,
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If(in_guard_time,
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If(buf_just_written,
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self.underflow.eq(1)
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).Else(
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fifo.we.eq(1)
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)
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),
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If(self.we & ~replace & ~any_error,
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fifo.we.eq(1)
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)
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)
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# Buffer write
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# Must come after read to handle concurrent read+write properly
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self.sync.rsys += [
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buf_just_written.eq(0),
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If(self.we & ~any_error,
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buf_just_written.eq(1),
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buf_pending.eq(1),
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buf.eq(self.ev)
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)
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]
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self.comb += self.writable.eq(fifo.writable)
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# Buffer output of FIFO to improve timing
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dout_stb = Signal()
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dout_ack = Signal()
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dout = Record(ev_layout)
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self.sync.rio += \
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If(fifo.re,
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dout_stb.eq(1),
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dout.eq(fifo_out)
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).Elif(dout_ack,
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dout_stb.eq(0)
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)
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self.comb += fifo.re.eq(fifo.readable & (~dout_stb | dout_ack))
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# latency compensation
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if interface.delay:
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counter_rtio = Signal.like(counter.value_rtio)
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self.sync.rtio += counter_rtio.eq(counter.value_rtio -
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interface.delay + 1)
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else:
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counter_rtio = counter.value_rtio
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# FIFO read through buffer
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self.comb += [
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dout_ack.eq(
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dout.timestamp[fine_ts_width:] == counter_rtio),
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interface.stb.eq(dout_stb & dout_ack)
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]
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busy_transfer = BlindTransfer()
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self.submodules += busy_transfer
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self.comb += [
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busy_transfer.i.eq(interface.stb & interface.busy),
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self.busy.eq(busy_transfer.o),
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]
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if data_width:
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self.comb += interface.data.eq(dout.data)
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if address_width:
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self.comb += interface.address.eq(dout.address)
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if fine_ts_width:
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self.comb += interface.fine_ts.eq(dout.timestamp[:fine_ts_width])
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class _InputManager(Module):
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def __init__(self, interface, counter, fifo_depth):
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data_width = rtlink.get_data_width(interface)
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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ev_layout = []
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if data_width:
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ev_layout.append(("data", data_width))
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if interface.timestamped:
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ev_layout.append(("timestamp", counter.width + fine_ts_width))
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self.ev = Record(ev_layout)
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal() # pulsed
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# # #
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fifo = ClockDomainsRenamer({"read": "rsys", "write": "rio"})(
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AsyncFIFO(layout_len(ev_layout), fifo_depth))
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self.submodules += fifo
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fifo_in = Record(ev_layout)
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fifo_out = Record(ev_layout)
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self.comb += [
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout)
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]
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# latency compensation
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if interface.delay:
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counter_rtio = Signal.like(counter.value_rtio)
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self.sync.rtio += counter_rtio.eq(counter.value_rtio -
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interface.delay + 1)
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else:
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counter_rtio = counter.value_rtio
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# FIFO write
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if data_width:
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self.comb += fifo_in.data.eq(interface.data)
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if interface.timestamped:
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if fine_ts_width:
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full_ts = Cat(interface.fine_ts, counter_rtio)
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else:
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full_ts = counter_rtio
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self.comb += fifo_in.timestamp.eq(full_ts)
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self.comb += fifo.we.eq(interface.stb)
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# FIFO read
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self.comb += [
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self.ev.eq(fifo_out),
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self.readable.eq(fifo.readable),
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fifo.re.eq(self.re)
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]
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overflow_transfer = BlindTransfer()
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self.submodules += overflow_transfer
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self.comb += [
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overflow_transfer.i.eq(fifo.we & ~fifo.writable),
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self.overflow.eq(overflow_transfer.o),
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]
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class Channel:
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def __init__(self, interface, probes=None, overrides=None,
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ofifo_depth=64, ififo_depth=64):
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if probes is None:
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probes = []
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if overrides is None:
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overrides = []
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self.interface = interface
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self.probes = probes
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self.overrides = overrides
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self.ofifo_depth = ofifo_depth
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self.ififo_depth = ififo_depth
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@classmethod
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def from_phy(cls, phy, **kwargs):
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probes = getattr(phy, "probes", [])
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overrides = getattr(phy, "overrides", [])
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return cls(phy.rtlink, probes, overrides, **kwargs)
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class LogChannel:
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"""A degenerate channel used to log messages into the analyzer."""
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def __init__(self):
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self.interface = rtlink.Interface(rtlink.OInterface(32))
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self.probes = []
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self.overrides = []
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class Core(Module, AutoCSR):
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def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
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if fine_ts_width is None:
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fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
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for c in channels)
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self.cri = cri.Interface()
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self.reset = CSR()
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self.reset_phy = CSR()
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self.async_error = CSR(2)
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self.comb += self.cri.arb_gnt.eq(1)
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# Clocking/Reset
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# Create rsys, rio and rio_phy domains based on sys and rtio
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# with reset controlled by CRI.
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cmd_reset = Signal(reset=1)
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cmd_reset_phy = Signal(reset=1)
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self.sync += [
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cmd_reset.eq(self.reset.re),
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cmd_reset_phy.eq(self.reset_phy.re)
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]
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cmd_reset.attr.add("no_retiming")
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cmd_reset_phy.attr.add("no_retiming")
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(cmd_reset)
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio, cmd_reset)
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self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio_phy, cmd_reset_phy)
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# Managers
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self.submodules.counter = RTIOCounter(len(self.cri.timestamp) - fine_ts_width)
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# Collision is not an asynchronous error with local RTIO, but
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# we treat it as such for consistency with DRTIO, where collisions
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# are reported by the satellites.
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o_underflow = Signal()
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o_sequence_error = Signal()
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o_collision = Signal()
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o_busy = Signal()
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self.sync.rsys += [
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If(self.cri.cmd == cri.commands["write"],
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o_underflow.eq(0),
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o_sequence_error.eq(0),
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),
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If(self.async_error.re,
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If(self.async_error.r[0], o_collision.eq(0)),
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If(self.async_error.r[1], o_busy.eq(0)),
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)
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]
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o_statuses, i_statuses = [], []
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i_datas, i_timestamps = [], []
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i_ack = Signal()
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sel = self.cri.chan_sel[:16]
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for n, channel in enumerate(channels):
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if isinstance(channel, LogChannel):
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o_statuses.append(1)
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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continue
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selected = Signal()
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self.comb += selected.eq(sel == n)
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o_manager = _OutputManager(channel.interface.o, self.counter,
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channel.ofifo_depth, guard_io_cycles)
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self.submodules += o_manager
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if hasattr(o_manager.ev, "data"):
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self.comb += o_manager.ev.data.eq(self.cri.o_data)
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if hasattr(o_manager.ev, "address"):
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self.comb += o_manager.ev.address.eq(self.cri.o_address)
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ts_shift = len(self.cri.timestamp) - len(o_manager.ev.timestamp)
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self.comb += o_manager.ev.timestamp.eq(self.cri.timestamp[ts_shift:])
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self.comb += o_manager.we.eq(selected & (self.cri.cmd == cri.commands["write"]))
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self.sync.rsys += [
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If(o_manager.underflow, o_underflow.eq(1)),
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If(o_manager.sequence_error, o_sequence_error.eq(1)),
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If(o_manager.collision, o_collision.eq(1)),
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If(o_manager.busy, o_busy.eq(1))
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]
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o_statuses.append(o_manager.writable)
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if channel.interface.i is not None:
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i_manager = _InputManager(channel.interface.i, self.counter,
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channel.ififo_depth)
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self.submodules += i_manager
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if hasattr(i_manager.ev, "data"):
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i_datas.append(i_manager.ev.data)
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else:
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i_datas.append(0)
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if channel.interface.i.timestamped:
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ts_shift = (len(self.cri.i_timestamp) - len(i_manager.ev.timestamp))
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i_timestamps.append(i_manager.ev.timestamp << ts_shift)
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else:
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i_timestamps.append(0)
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overflow = Signal()
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self.sync.rsys += [
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If(selected & i_ack,
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overflow.eq(0)),
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If(i_manager.overflow,
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overflow.eq(1))
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]
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self.comb += i_manager.re.eq(selected & i_ack & ~overflow)
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i_statuses.append(Cat(i_manager.readable & ~overflow, overflow))
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else:
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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o_status_raw = Signal()
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self.comb += [
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o_status_raw.eq(Array(o_statuses)[sel]),
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self.cri.o_status.eq(Cat(
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~o_status_raw, o_underflow, o_sequence_error)),
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self.async_error.w.eq(Cat(o_collision, o_busy))
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]
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i_status_raw = Signal(2)
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self.comb += i_status_raw.eq(Array(i_statuses)[sel])
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input_timeout = Signal.like(self.cri.timestamp)
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input_pending = Signal()
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self.sync.rsys += [
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i_ack.eq(0),
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If(i_ack,
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self.cri.i_status.eq(Cat(~i_status_raw[0], i_status_raw[1], 0)),
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self.cri.i_data.eq(Array(i_datas)[sel]),
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self.cri.i_timestamp.eq(Array(i_timestamps)[sel]),
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),
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If((self.cri.counter >= input_timeout) | (i_status_raw != 0),
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If(input_pending, i_ack.eq(1)),
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input_pending.eq(0)
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),
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If(self.cri.cmd == cri.commands["read"],
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input_timeout.eq(self.cri.timestamp),
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input_pending.eq(1),
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self.cri.i_status.eq(0b100)
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)
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]
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self.comb += self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
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