mirror of https://github.com/m-labs/artiq.git
302 lines
11 KiB
Python
302 lines
11 KiB
Python
"""Real-time controller for master"""
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.cdc import RTIOCounter
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from artiq.gateware.rtio import cri
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class _CSRs(AutoCSR):
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def __init__(self):
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self.chan_sel_override = CSRStorage(16)
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self.chan_sel_override_en = CSRStorage()
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self.tsc_correction = CSRStorage(64)
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self.set_time = CSR()
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self.underflow_margin = CSRStorage(16, reset=200)
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self.reset = CSR()
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self.reset_phy = CSR()
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self.o_get_fifo_space = CSR()
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self.o_dbg_fifo_space = CSRStatus(16)
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self.o_dbg_last_timestamp = CSRStatus(64)
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self.o_dbg_fifo_space_req_cnt = CSRStatus(32)
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self.o_reset_channel_status = CSR()
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self.o_wait = CSRStatus()
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self.o_fifo_space_timeout = CSR()
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class RTController(Module):
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def __init__(self, rt_packet, channel_count, fine_ts_width):
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self.csrs = _CSRs()
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self.cri = cri.Interface()
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self.comb += self.cri.arb_gnt.eq(1)
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# channel selection
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chan_sel = Signal(16)
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self.comb += chan_sel.eq(
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Mux(self.csrs.chan_sel_override_en.storage,
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self.csrs.chan_sel_override.storage,
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self.cri.chan_sel[:16]))
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# master RTIO counter and counter synchronization
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self.submodules.counter = RTIOCounter(64-fine_ts_width)
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self.comb += self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
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tsc_correction = Signal(64)
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self.csrs.tsc_correction.storage.attr.add("no_retiming")
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self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
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self.comb += [
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rt_packet.tsc_value.eq(
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self.counter.value_rtio + tsc_correction),
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self.csrs.set_time.w.eq(rt_packet.set_time_stb)
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]
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self.sync += [
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If(rt_packet.set_time_ack, rt_packet.set_time_stb.eq(0)),
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If(self.csrs.set_time.re, rt_packet.set_time_stb.eq(1))
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]
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# reset
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self.sync += [
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If(rt_packet.reset_ack, rt_packet.reset_stb.eq(0)),
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If(self.csrs.reset.re,
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rt_packet.reset_stb.eq(1),
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rt_packet.reset_phy.eq(0)
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),
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If(self.csrs.reset_phy.re,
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rt_packet.reset_stb.eq(1),
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rt_packet.reset_phy.eq(1)
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),
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]
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local_reset = Signal(reset=1)
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self.sync += local_reset.eq(self.csrs.reset.re)
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local_reset.attr.add("no_retiming")
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self.clock_domains.cd_sys_with_rst = ClockDomain()
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self.clock_domains.cd_rtio_with_rst = ClockDomain()
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self.comb += [
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self.cd_sys_with_rst.clk.eq(ClockSignal()),
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self.cd_sys_with_rst.rst.eq(local_reset)
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]
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self.comb += self.cd_rtio_with_rst.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(self.cd_rtio_with_rst, local_reset)
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# remote channel status cache
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fifo_spaces_mem = Memory(16, channel_count)
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fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)
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self.specials += fifo_spaces_mem, fifo_spaces
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last_timestamps_mem = Memory(64, channel_count)
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last_timestamps = last_timestamps_mem.get_port(write_capable=True)
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self.specials += last_timestamps_mem, last_timestamps
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# common packet fields
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rt_packet_fifo_request = Signal()
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rt_packet_read_request = Signal()
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self.comb += [
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fifo_spaces.adr.eq(chan_sel),
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last_timestamps.adr.eq(chan_sel),
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last_timestamps.dat_w.eq(self.cri.timestamp),
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rt_packet.sr_channel.eq(chan_sel),
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rt_packet.sr_address.eq(self.cri.o_address),
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rt_packet.sr_data.eq(self.cri.o_data),
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rt_packet.sr_timestamp.eq(self.cri.timestamp),
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If(rt_packet_fifo_request,
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rt_packet.sr_notwrite.eq(1),
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rt_packet.sr_address.eq(0)
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),
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If(rt_packet_read_request,
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rt_packet.sr_notwrite.eq(1),
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rt_packet.sr_address.eq(1)
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)
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]
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# output status
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o_status_wait = Signal()
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o_status_underflow = Signal()
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o_status_sequence_error = Signal()
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self.comb += [
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self.cri.o_status.eq(Cat(
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o_status_wait, o_status_underflow, o_status_sequence_error)),
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self.csrs.o_wait.status.eq(o_status_wait)
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]
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o_sequence_error_set = Signal()
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o_underflow_set = Signal()
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self.sync.sys_with_rst += [
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If(self.cri.cmd == cri.commands["write"],
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o_status_underflow.eq(0),
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o_status_sequence_error.eq(0),
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),
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If(o_underflow_set, o_status_underflow.eq(1)),
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If(o_sequence_error_set, o_status_sequence_error.eq(1))
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]
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signal_fifo_space_timeout = Signal()
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self.sync.sys_with_rst += [
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If(self.csrs.o_fifo_space_timeout.re, self.csrs.o_fifo_space_timeout.w.eq(0)),
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If(signal_fifo_space_timeout, self.csrs.o_fifo_space_timeout.w.eq(1))
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]
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timeout_counter = WaitTimer(8191)
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self.submodules += timeout_counter
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# TODO: collision, replace, busy
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cond_sequence_error = self.cri.timestamp < last_timestamps.dat_r
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cond_underflow = ((self.cri.timestamp[fine_ts_width:]
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- self.csrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
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# input status
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i_status_wait_event = Signal()
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i_status_overflow = Signal()
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i_status_wait_status = Signal()
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self.comb += self.cri.i_status.eq(Cat(
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i_status_wait_event, i_status_overflow, i_status_wait_status))
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load_read_reply = Signal()
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self.sync.sys_with_rst += [
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If(load_read_reply,
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i_status_wait_event.eq(0),
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i_status_overflow.eq(0),
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If(rt_packet.read_no_event,
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If(rt_packet.read_is_overflow,
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i_status_overflow.eq(1)
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).Else(
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i_status_wait_event.eq(1)
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)
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),
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self.cri.i_data.eq(rt_packet.read_data),
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self.cri.i_timestamp.eq(rt_packet.read_timestamp)
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)
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]
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# FSM
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fsm = ClockDomainsRenamer("sys_with_rst")(FSM())
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.cri.cmd == cri.commands["write"],
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If(cond_sequence_error,
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o_sequence_error_set.eq(1)
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).Elif(cond_underflow,
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o_underflow_set.eq(1)
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).Else(
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NextState("WRITE")
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)
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),
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If(self.cri.cmd == cri.commands["read"], NextState("READ")),
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If(self.csrs.o_get_fifo_space.re, NextState("GET_FIFO_SPACE"))
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)
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fsm.act("WRITE",
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o_status_wait.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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fifo_spaces.we.eq(1),
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fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1),
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last_timestamps.we.eq(1),
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If(fifo_spaces.dat_r <= 1,
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NextState("GET_FIFO_SPACE")
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).Else(
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NextState("IDLE")
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)
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)
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)
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fsm.act("GET_FIFO_SPACE",
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o_status_wait.eq(1),
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rt_packet.fifo_space_not_ack.eq(1),
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rt_packet_fifo_request.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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NextState("GET_FIFO_SPACE_REPLY")
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)
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)
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fsm.act("GET_FIFO_SPACE_REPLY",
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o_status_wait.eq(1),
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fifo_spaces.dat_w.eq(rt_packet.fifo_space),
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fifo_spaces.we.eq(1),
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rt_packet.fifo_space_not_ack.eq(1),
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If(rt_packet.fifo_space_not,
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If(rt_packet.fifo_space != 0,
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NextState("IDLE")
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).Else(
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NextState("GET_FIFO_SPACE")
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)
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),
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timeout_counter.wait.eq(1),
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If(timeout_counter.done,
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signal_fifo_space_timeout.eq(1),
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NextState("GET_FIFO_SPACE")
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)
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)
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fsm.act("READ",
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i_status_wait_status.eq(1),
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rt_packet.read_not_ack.eq(1),
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rt_packet_read_request.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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NextState("GET_READ_REPLY")
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)
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)
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fsm.act("GET_READ_REPLY",
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i_status_wait_status.eq(1),
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rt_packet.read_not_ack.eq(1),
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If(rt_packet.read_not,
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load_read_reply.eq(1),
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NextState("IDLE")
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)
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)
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# channel state access
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self.comb += [
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self.csrs.o_dbg_fifo_space.status.eq(fifo_spaces.dat_r),
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self.csrs.o_dbg_last_timestamp.status.eq(last_timestamps.dat_r),
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If(self.csrs.o_reset_channel_status.re,
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fifo_spaces.dat_w.eq(0),
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fifo_spaces.we.eq(1),
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last_timestamps.dat_w.eq(0),
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last_timestamps.we.eq(1)
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)
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]
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self.sync += \
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If((rt_packet.sr_stb & rt_packet.sr_ack & rt_packet_fifo_request),
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self.csrs.o_dbg_fifo_space_req_cnt.status.eq(
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self.csrs.o_dbg_fifo_space_req_cnt.status + 1)
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)
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def get_csrs(self):
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return self.csrs.get_csrs()
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class RTManager(Module, AutoCSR):
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def __init__(self, rt_packet):
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self.request_echo = CSR()
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self.packet_err_present = CSR()
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self.packet_err_code = CSRStatus(8)
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self.update_packet_cnt = CSR()
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self.packet_cnt_tx = CSRStatus(32)
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self.packet_cnt_rx = CSRStatus(32)
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# # #
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self.comb += self.request_echo.w.eq(rt_packet.echo_stb)
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self.sync += [
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If(rt_packet.echo_ack, rt_packet.echo_stb.eq(0)),
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If(self.request_echo.re, rt_packet.echo_stb.eq(1))
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]
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self.comb += [
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self.packet_err_present.w.eq(rt_packet.error_not),
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rt_packet.error_not_ack.eq(self.packet_err_present.re),
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self.packet_err_code.status.eq(rt_packet.error_code)
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]
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self.sync += \
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If(self.update_packet_cnt.re,
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self.packet_cnt_tx.status.eq(rt_packet.packet_cnt_tx),
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self.packet_cnt_rx.status.eq(rt_packet.packet_cnt_rx)
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)
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