mirror of https://github.com/m-labs/artiq.git
71 lines
2.6 KiB
Python
71 lines
2.6 KiB
Python
import unittest
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import random
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from migen import *
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from misoc.interconnect.wishbone import SRAM
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from misoc.interconnect.stream import Converter
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from artiq.gateware.serwb import packet
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from artiq.gateware.serwb import etherbone
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class DUT(Module):
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def __init__(self):
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# wishbone slave
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slave_depacketizer = packet.Depacketizer(int(100e6))
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slave_packetizer = packet.Packetizer()
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self.submodules += slave_depacketizer, slave_packetizer
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slave_etherbone = etherbone.Etherbone(mode="slave")
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self.submodules += slave_etherbone
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self.comb += [
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slave_depacketizer.source.connect(slave_etherbone.sink),
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slave_etherbone.source.connect(slave_packetizer.sink)
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]
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# wishbone master
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master_depacketizer = packet.Depacketizer(int(100e6))
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master_packetizer = packet.Packetizer()
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self.submodules += master_depacketizer, master_packetizer
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master_etherbone = etherbone.Etherbone(mode="master")
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master_sram = SRAM(64, bus=master_etherbone.wishbone.bus)
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self.submodules += master_etherbone, master_sram
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self.comb += [
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master_depacketizer.source.connect(master_etherbone.sink),
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master_etherbone.source.connect(master_packetizer.sink)
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]
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# connect core directly with converters in the loop
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s2m_downconverter = Converter(32, 16)
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s2m_upconverter = Converter(16, 32)
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self.submodules += s2m_downconverter, s2m_upconverter
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m2s_downconverter = Converter(32, 16)
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m2s_upconverter = Converter(16, 32)
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self.submodules += m2s_upconverter, m2s_downconverter
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self.comb += [
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slave_packetizer.source.connect(s2m_downconverter.sink),
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s2m_downconverter.source.connect(s2m_upconverter.sink),
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s2m_upconverter.source.connect(master_depacketizer.sink),
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master_packetizer.source.connect(m2s_downconverter.sink),
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m2s_downconverter.source.connect(m2s_upconverter.sink),
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m2s_upconverter.source.connect(slave_depacketizer.sink)
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]
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# expose wishbone slave
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self.wishbone = slave_etherbone.wishbone.bus
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class TestEtherbone(unittest.TestCase):
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def test_write_read_sram(self):
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dut = DUT()
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prng = random.Random(1)
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def generator(dut):
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datas = [prng.randrange(0, 2**32-1) for i in range(16)]
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for i in range(16):
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yield from dut.wishbone.write(i, datas[i])
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for i in range(16):
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data = (yield from dut.wishbone.read(i))
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self.assertEqual(data, datas[i])
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run_simulation(dut, generator(dut))
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