mirror of https://github.com/m-labs/artiq.git
76 lines
2.2 KiB
Python
76 lines
2.2 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.cdc import MultiReg
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class RTIOBankO(Module):
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def __init__(self, channels, counter_width, fifo_depth):
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self.sel = Signal(max=len(channels))
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self.timestamp = Signal(counter_width)
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self.value = Signal()
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self.writable = Signal()
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self.we = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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###
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counter = Signal(counter_width)
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self.sync += [
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counter.eq(counter + 1),
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If(self.we & self.writable,
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If(self.timestamp < counter + 2, self.underflow.eq(1))
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)
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]
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fifos = []
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for n, channel in enumerate(channels):
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fifo = SyncFIFOBuffered([
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("timestamp", counter_width), ("value", 1)],
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fifo_depth)
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self.submodules += fifo
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fifos.append(fifo)
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# FIFO write
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self.comb += [
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fifo.din.timestamp.eq(self.timestamp),
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fifo.din.value.eq(self.value),
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fifo.we.eq(self.we & (self.sel == n))
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]
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# FIFO read
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time_hit = Signal()
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self.comb += [
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time_hit.eq(fifo.readable &
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(fifo.dout.timestamp == counter)),
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fifo.re.eq(time_hit)
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]
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self.sync += If(time_hit, channel.eq(fifo.dout.value))
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selfifo = Array(fifos)[self.sel]
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self.comb += self.writable.eq(selfifo.writable), self.level.eq(selfifo.level)
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class RTIO(Module, AutoCSR):
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def __init__(self, channels, counter_width=32, ofifo_depth=8, ififo_depth=8):
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self.submodules.bank_o = InsertReset(RTIOBankO(channels, counter_width, ofifo_depth))
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_o_timestamp = CSRStorage(counter_width)
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self._r_o_value = CSRStorage()
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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self.comb += [
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self.bank_o.reset.eq(self._r_reset.storage),
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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self._r_o_writable.status.eq(self.bank_o.writable),
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self.bank_o.we.eq(self._r_o_we.re),
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self._r_o_underflow.status.eq(self.bank_o.underflow),
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self._r_o_level.status.eq(self.bank_o.level)
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]
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