artiq/artiq/gateware/drtio/transceiver
Florent Kermarrec 5b3d6d57e2 drtio/gth: power down rx on restart (seems to make link initialization reliable) 2018-03-06 11:49:28 +01:00
..
__init__.py drtio: GTX WIP 2016-10-14 00:36:13 +08:00
clock_aligner.py add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
gth_ultrascale.py drtio/gth: power down rx on restart (seems to make link initialization reliable) 2018-03-06 11:49:28 +01:00
gth_ultrascale_init.py drtio/gth: cleanup import 2018-03-06 10:56:07 +01:00
gtp_7series.py drtio/transceiver/gtp: implement tx multi lane phase alignment sequence 2018-02-27 12:32:25 +01:00
gtp_7series_init.py drtio/transceiver/gtp: implement tx multi lane phase alignment sequence 2018-02-27 12:32:25 +01:00