mirror of https://github.com/m-labs/artiq.git
130 lines
3.9 KiB
Python
130 lines
3.9 KiB
Python
import unittest
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from types import SimpleNamespace
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from migen import *
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from artiq.gateware.drtio.link_layer import *
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def process(seq):
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dut = Scrambler(8)
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rseq = []
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def pump():
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yield dut.i.eq(seq[0])
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yield
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for w in seq[1:]:
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yield dut.i.eq(w)
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yield
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rseq.append((yield dut.o))
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yield
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rseq.append((yield dut.o))
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run_simulation(dut, pump())
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return rseq
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class Loopback(Module):
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def __init__(self, nwords):
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ks = [Signal() for k in range(nwords)]
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ds = [Signal(8) for d in range(nwords)]
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encoder = SimpleNamespace(k=ks, d=ds)
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decoders = [SimpleNamespace(k=k, d=d) for k, d in zip(ks, ds)]
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self.submodules.tx = LinkLayerTX(encoder)
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self.submodules.rx = LinkLayerRX(decoders)
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class TestLinkLayer(unittest.TestCase):
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def test_packets(self):
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dut = Loopback(4)
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def scrambler_sync():
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for i in range(8):
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yield
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rt_packets = [
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[0x12459970, 0x9938cdef, 0x12340000],
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[0xabcdef00, 0x12345678],
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[0xeeeeeeee, 0xffffffff, 0x01020304, 0x11223344],
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[0x88277475, 0x19883332, 0x19837662, 0x81726668, 0x81876261]
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]
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def transmit_rt_packets():
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yield from scrambler_sync()
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for packet in rt_packets:
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yield dut.tx.rt_frame.eq(1)
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for data in packet:
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yield dut.tx.rt_data.eq(data)
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yield
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yield dut.tx.rt_frame.eq(0)
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yield
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# flush
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for i in range(20):
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yield
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rx_rt_packets = []
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@passive
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def receive_rt_packets():
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yield from scrambler_sync()
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previous_frame = 0
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while True:
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frame = yield dut.rx.rt_frame
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if frame and not previous_frame:
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packet = []
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rx_rt_packets.append(packet)
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previous_frame = frame
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if frame:
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packet.append((yield dut.rx.rt_data))
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yield
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aux_packets = [
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[0x12, 0x34],
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[0x44, 0x11, 0x98, 0x78],
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[0xbb, 0xaa, 0xdd, 0xcc, 0x00, 0xff, 0xee]
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]
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def transmit_aux_packets():
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yield from scrambler_sync()
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for packet in aux_packets:
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yield dut.tx.aux_frame.eq(1)
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for data in packet:
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yield dut.tx.aux_data.eq(data)
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yield
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while not (yield dut.tx.aux_ack):
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yield
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yield dut.tx.aux_frame.eq(0)
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yield
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while not (yield dut.tx.aux_ack):
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yield
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# flush
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for i in range(20):
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yield
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rx_aux_packets = []
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@passive
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def receive_aux_packets():
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yield from scrambler_sync()
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previous_frame = 0
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while True:
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if (yield dut.rx.aux_stb):
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frame = yield dut.rx.aux_frame
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if frame and not previous_frame:
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packet = []
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rx_aux_packets.append(packet)
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previous_frame = frame
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if frame:
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packet.append((yield dut.rx.aux_data))
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yield
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run_simulation(dut, [transmit_rt_packets(), receive_rt_packets(),
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transmit_aux_packets(), receive_aux_packets()])
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# print("RT:")
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# for packet in rx_rt_packets:
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# print(" ".join("{:08x}".format(x) for x in packet))
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# print("AUX:")
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# for packet in rx_aux_packets:
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# print(" ".join("{:02x}".format(x) for x in packet))
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self.assertEqual(rt_packets, rx_rt_packets)
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self.assertEqual(aux_packets, rx_aux_packets)
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