mirror of https://github.com/m-labs/artiq.git
132 lines
4.7 KiB
Python
132 lines
4.7 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.ppro import BaseSoC
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from artiq.gateware import rtio, ad9858, nist_qc1
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from artiq.gateware.rtio.phy import ttl_simple
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class _TestGen(Module):
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def __init__(self, pad):
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divc = Signal(15)
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ce = Signal()
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self.sync += Cat(divc, ce).eq(divc + 1)
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sr = Signal(8, reset=0b10101000)
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self.sync += If(ce, sr.eq(Cat(sr[1:], sr[0])))
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self.comb += pad.eq(sr[0])
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class _RTIOMiniCRG(Module, AutoCSR):
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def __init__(self, platform):
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self._clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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# 80MHz -> 125MHz
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rtio_internal_clk = Signal()
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self.specials += Instance("DCM_CLKGEN",
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p_CLKFXDV_DIVIDE=2,
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p_CLKFX_DIVIDE=16, p_CLKFX_MD_MAX=1.6, p_CLKFX_MULTIPLY=25,
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p_CLKIN_PERIOD=12.5, p_SPREAD_SPECTRUM="NONE",
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p_STARTUP_WAIT="FALSE",
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i_CLKIN=ClockSignal(), o_CLKFX=rtio_internal_clk,
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i_FREEZEDCM=0, i_RST=ResetSignal())
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rtio_external_clk = platform.request("xtrig")
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platform.add_period_constraint(rtio_external_clk, 8.0)
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_S=self._clock_sel.storage,
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o_O=self.cd_rtio.clk)
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platform.add_platform_command("""
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NET "{int_clk}" TNM_NET = "GRPint_clk";
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NET "{ext_clk}" TNM_NET = "GRPext_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
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TIMESPEC "TSfix_ise3" = FROM "GRPext_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
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TIMESPEC "TSfix_ise5" = FROM "GRPext_clk" TO "GRPint_clk" TIG;
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TIMESPEC "TSfix_ise6" = FROM "GRPint_clk" TO "GRPext_clk" TIG;
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""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
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class UP(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, cpu_type="or1k",
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with_test_gen=False, **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type,
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sdram_controller_settings=MiniconSettings(),
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**kwargs)
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platform.add_extension(nist_qc1.papilio_adapter_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("ext_led", 0)))
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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# RTIO channels
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rtio_channels = []
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for i in range(2):
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phy = ttl_simple.Inout(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink))
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for i in range(5):
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink))
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fud = Signal()
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self.add_constant("RTIO_FUD_CHANNEL", len(rtio_channels))
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phy = ttl_simple.Output(fud)
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink))
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# RTIO core
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self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000,
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counter_width=32)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000,
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32, rtio_csrs)
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if with_test_gen:
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self.submodules.test_gen = _TestGen(platform.request("ttl", 8))
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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self.comb += dds_pads.fud_n.eq(~fud)
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default_subtarget = UP
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