mirror of https://github.com/m-labs/artiq.git
84 lines
3.9 KiB
ReStructuredText
84 lines
3.9 KiB
ReStructuredText
Core device
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===========
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The core device is a FPGA-based hardware component that contains a softcore CPU tightly coupled with the so-called RTIO core that provides precision timing. The CPU executes Python code that is statically compiled by the ARTIQ compiler, and communicates with the core device peripherals (TTL, DDS, etc.) over the RTIO core. This architecture provides high timing resolution, low latency, low jitter, high level programming capabilities, and good integration with the rest of the Python experiment code.
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While it is possible to use all the other parts of ARTIQ (controllers, master, GUI, dataset management, etc.) without a core device, many experiments require it.
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.. _core-device-flash-storage:
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Flash storage
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*************
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The core device contains some flash space that can be used to store configuration data.
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This storage area is used to store the core device MAC address, IP address and even the idle kernel.
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The flash storage area is one sector (typically 64 kB) large and is organized as a list of key-value records.
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This flash storage space can be accessed by using ``artiq_coreconfig`` (see: :ref:`core-device-configuration-tool`).
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.. _board-ports:
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FPGA board ports
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****************
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KC705
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-----
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST QC2 hardware (FMC).
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With the QC1 hardware, the TTL lines are mapped as follows:
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+--------------+------------+--------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+==============+
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| 0 | PMT0 | Input |
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+--------------+------------+--------------+
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| 1 | PMT1 | Input |
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+--------------+------------+--------------+
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| 2-16 | TTL0-14 | Output |
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+--------------+------------+--------------+
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| 17 | SMA_GPIO_N | Input+Output |
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+--------------+------------+--------------+
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| 18 | LED | Output |
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+--------------+------------+--------------+
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| 19 | TTL15 | Clock |
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+--------------+------------+--------------+
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Pipistrello
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-----------
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The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alternative. The current USB over serial protocol also suffers from limitations (no monitoring/injection, no idle experiment, no kernel interruptions, lack of robustness).
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When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows:
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+--------------+------------+------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+============+
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| 0 | PMT0 | Input |
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+--------------+------------+------------+
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| 1 | PMT1 | Input |
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+--------------+------------+------------+
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| 2-16 | TTL0-14 | Output |
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+--------------+------------+------------+
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| 17 | EXT_LED | Output |
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+--------------+------------+------------+
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| 18 | USER_LED_1 | Output |
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+--------------+------------+------------+
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| 19 | USER_LED_2 | Output |
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+--------------+------------+------------+
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| 20 | USER_LED_3 | Output |
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+--------------+------------+------------+
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| 21 | USER_LED_4 | Output |
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+--------------+------------+------------+
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| 22 | TTL15 | Clock |
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+--------------+------------+------------+
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The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
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The board can accept an external RTIO clock connected to PMT2. If the DDS box
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does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output
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on the adapter board onto C:15 disconnecting PMT2.
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