mirror of https://github.com/m-labs/artiq.git
106 lines
3.5 KiB
Python
106 lines
3.5 KiB
Python
from migen import *
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from artiq.gateware.rtio.sed import layouts
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from artiq.gateware.rtio.sed.lane_distributor import *
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from artiq.gateware.rtio.sed.fifos import *
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from artiq.gateware.rtio.sed.gates import *
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from artiq.gateware.rtio.sed.output_driver import *
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__all__ = ["SED"]
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class SED(Module):
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def __init__(self, channels, glbl_fine_ts_width, mode,
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lane_count=8, fifo_depth=128, enable_spread=True,
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quash_channels=[], report_buffer_space=False, interface=None):
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if mode == "sync":
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lane_dist_cdr = lambda x: x
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fifos_cdr = lambda x: x
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gates_cdr = lambda x: x
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output_driver_cdr = lambda x: x
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elif mode == "async":
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lane_dist_cdr = ClockDomainsRenamer("rsys")
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fifos_cdr = ClockDomainsRenamer({"write": "rsys", "read": "rio"})
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gates_cdr = ClockDomainsRenamer("rio")
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output_driver_cdr = ClockDomainsRenamer("rio")
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else:
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raise ValueError
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seqn_width = layouts.seqn_width(lane_count, fifo_depth)
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self.submodules.lane_dist = lane_dist_cdr(
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LaneDistributor(lane_count, seqn_width,
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layouts.fifo_payload(channels),
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[channel.interface.o.delay for channel in channels],
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glbl_fine_ts_width,
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enable_spread=enable_spread,
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quash_channels=quash_channels,
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interface=interface))
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self.submodules.fifos = fifos_cdr(
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FIFOs(lane_count, fifo_depth,
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layouts.fifo_payload(channels), mode, report_buffer_space))
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self.submodules.gates = gates_cdr(
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Gates(lane_count, seqn_width,
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layouts.fifo_payload(channels),
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layouts.output_network_payload(channels, glbl_fine_ts_width)))
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self.submodules.output_driver = output_driver_cdr(
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OutputDriver(channels, glbl_fine_ts_width, lane_count, seqn_width))
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for o, i in zip(self.lane_dist.output, self.fifos.input):
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self.comb += o.connect(i)
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for o, i in zip(self.fifos.output, self.gates.input):
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self.comb += o.connect(i)
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for o, i in zip(self.gates.output, self.output_driver.input):
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self.comb += i.eq(o)
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if report_buffer_space:
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self.comb += [
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self.cri.o_buffer_space_valid.eq(1),
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self.cri.o_buffer_space.eq(self.fifos.buffer_space)
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]
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@property
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def cri(self):
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return self.lane_dist.cri
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# in CRI clock domain
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@property
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def minimum_coarse_timestamp(self):
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return self.lane_dist.minimum_coarse_timestamp
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# in I/O clock domain
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@property
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def coarse_timestamp(self):
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return self.gates.coarse_timestamp
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# in CRI clock domain
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@property
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def sequence_error(self):
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return self.lane_dist.sequence_error
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# in CRI clock domain
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@property
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def sequence_error_channel(self):
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return self.lane_dist.sequence_error_channel
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# in I/O clock domain
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@property
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def collision(self):
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return self.output_driver.collision
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# in I/O clock domain
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@property
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def collision_channel(self):
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return self.output_driver.collision_channel
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# in I/O clock domain
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@property
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def busy(self):
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return self.output_driver.busy
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# in I/O clock domain
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@property
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def busy_channel(self):
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return self.output_driver.busy_channel
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