mirror of https://github.com/m-labs/artiq.git
244 lines
8.7 KiB
Python
Executable File
244 lines
8.7 KiB
Python
Executable File
#!/usr/bin/env python3
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.build.platforms.sinara import sayma_rtm
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from misoc.interconnect import wishbone, stream
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from misoc.interconnect.csr import *
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from misoc.cores import identifier
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from misoc.cores import spi2
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from misoc.cores import gpio
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from misoc.integration.wb_slaves import WishboneSlaveManager
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from misoc.integration.cpu_interface import get_csr_csv
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from artiq.gateware import serwb
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from artiq import __version__ as artiq_version
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class CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.serwb_refclk = Signal()
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self.serwb_reset = Signal()
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serwb_refclk_bufr = Signal()
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serwb_refclk_bufg = Signal()
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self.specials += Instance("BUFR", i_I=self.serwb_refclk, o_O=serwb_refclk_bufr)
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self.specials += Instance("BUFG", i_I=serwb_refclk_bufr, o_O=serwb_refclk_bufg)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys4x = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0,
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p_CLKFBOUT_MULT_F=8, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=serwb_refclk_bufg, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 500MHz
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p_CLKOUT0_DIVIDE_F=2, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys4x,
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# 200MHz
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p_CLKOUT1_DIVIDE=5, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clk200
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),
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Instance("BUFR", p_BUFR_DIVIDE="4", i_I=pll_sys4x, o_O=self.cd_sys.clk),
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Instance("BUFIO", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | self.serwb_reset),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | self.serwb_reset)
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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class RTMMagic(Module, AutoCSR):
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def __init__(self):
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self.magic = CSRStatus(32)
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self.comb += self.magic.status.eq(0x5352544d) # "SRTM"
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class RTMScratch(Module, AutoCSR):
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def __init__(self):
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self.write_stb = write_stb = CSR()
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self.write_ack = write_ack = CSRStatus()
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self.write_data = write_data = CSRStorage(32)
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self.read_stb = read_stb = CSRStatus()
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self.read_ack = read_ack = CSR()
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self.read_data = read_data = CSRStatus(32)
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# # #
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fifo = stream.SyncFIFO([("data", 32)], 512, buffered=True)
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self.submodules += fifo
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self.comb += [
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# Connect registers to FIFO Sink
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fifo.sink.stb.eq(write_stb.re),
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write_ack.status.eq(fifo.sink.ack),
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fifo.sink.data.eq(write_data.storage),
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# Connect FIFO Source to registers
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read_stb.status.eq(fifo.source.stb),
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fifo.source.ack.eq(read_ack.re),
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read_data.status.eq(fifo.source.data)
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]
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CSR_RANGE_SIZE = 0x800
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class SaymaRTM(Module):
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def __init__(self, platform):
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csr_devices = []
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self.submodules.crg = CRG(platform)
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clk_freq = 125e6
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self.submodules.rtm_magic = RTMMagic()
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csr_devices.append("rtm_magic")
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self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
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csr_devices.append("rtm_identifier")
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self.submodules.rtm_scratch = RTMScratch()
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csr_devices.append("rtm_scratch")
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# clock mux: 100MHz ext SMA clock to HMC830 input
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self.submodules.clock_mux = gpio.GPIOOut(Cat(
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platform.request("clk_src_ext_sel"),
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platform.request("ref_clk_src_sel"),
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platform.request("dac_clk_src_sel"),
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platform.request("ref_lo_clk_sel")),
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reset_out=0b0111)
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csr_devices.append("clock_mux")
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# UART loopback
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serial = platform.request("serial")
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self.comb += serial.tx.eq(serial.rx)
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# Allaki: enable RF output, GPIO access to attenuator
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self.comb += [
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platform.request("allaki0_rfsw0").eq(1),
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platform.request("allaki0_rfsw1").eq(1),
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platform.request("allaki1_rfsw0").eq(1),
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platform.request("allaki1_rfsw1").eq(1),
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platform.request("allaki2_rfsw0").eq(1),
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platform.request("allaki2_rfsw1").eq(1),
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platform.request("allaki3_rfsw0").eq(1),
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platform.request("allaki3_rfsw1").eq(1),
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]
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allaki_atts = [
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platform.request("allaki0_att0"),
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platform.request("allaki0_att1"),
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platform.request("allaki1_att0"),
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platform.request("allaki1_att1"),
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platform.request("allaki2_att0"),
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platform.request("allaki2_att1"),
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platform.request("allaki3_att0"),
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platform.request("allaki3_att1"),
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]
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allaki_att_gpio = []
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for allaki_att in allaki_atts:
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allaki_att_gpio += [
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allaki_att.le,
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allaki_att.sin,
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allaki_att.clk,
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allaki_att.rst_n,
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]
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self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
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csr_devices.append("allaki_atts")
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# HMC clock chip and DAC control
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self.comb += [
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platform.request("ad9154_rst_n").eq(1),
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platform.request("ad9154_txen", 0).eq(0b11),
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platform.request("ad9154_txen", 1).eq(0b11)
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]
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
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platform.request("hmc_spi"),
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platform.request("ad9154_spi", 0),
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platform.request("ad9154_spi", 1)))
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csr_devices.append("converter_spi")
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self.submodules.hmc7043_reset = gpio.GPIOOut(
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platform.request("hmc7043_reset"), reset_out=1)
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csr_devices.append("hmc7043_reset")
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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platform.add_period_constraint(serwb_pads.clk_p, 8.)
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serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
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self.submodules.serwb_phy_rtm = serwb_phy_rtm
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self.comb += [
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self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
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self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
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]
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csr_devices.append("serwb_phy_rtm")
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serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master")
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self.submodules += serwb_core
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# process CSR devices and connect them to serwb
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self.csr_regions = []
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wb_slaves = WishboneSlaveManager(0x10000000)
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for i, name in enumerate(csr_devices):
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origin = i*CSR_RANGE_SIZE
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module = getattr(self, name)
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csrs = module.get_csrs()
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bank = wishbone.CSRBank(csrs)
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self.submodules += bank
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wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
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self.csr_regions.append((name, origin, 32, csrs))
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self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus,
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wb_slaves.get_interconnect_slaves(),
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register=True)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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parser.add_argument("--output-dir", default="artiq_sayma/rtm_gateware",
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help="output directory for generated "
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"source files and binaries")
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parser.add_argument("--no-compile-gateware", action="store_true",
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help="do not compile the gateware, only generate "
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"the CSR map")
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parser.add_argument("--csr-csv", default=None,
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help="store CSR map in CSV format into the "
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"specified file")
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args = parser.parse_args()
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platform = sayma_rtm.Platform()
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top = SaymaRTM(platform)
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os.makedirs(args.output_dir, exist_ok=True)
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with open(os.path.join(args.output_dir, "rtm_csr.csv"), "w") as f:
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f.write(get_csr_csv(top.csr_regions))
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if not args.no_compile_gateware:
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platform.build(top, build_dir=args.output_dir, build_name="rtm")
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if __name__ == "__main__":
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main()
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