mirror of https://github.com/m-labs/artiq
81 lines
2.1 KiB
Rust
81 lines
2.1 KiB
Rust
use core::fmt;
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use dyld;
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pub const KERNELCPU_EXEC_ADDRESS: usize = 0x45000000;
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pub const KERNELCPU_PAYLOAD_ADDRESS: usize = 0x45060000;
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pub const KERNELCPU_LAST_ADDRESS: usize = 0x4fffffff;
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pub const KSUPPORT_HEADER_SIZE: usize = 0x80;
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#[derive(Debug)]
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pub enum Message<'a> {
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LoadRequest(&'a [u8]),
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LoadReply(Result<(), dyld::Error<'a>>),
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RtioInitRequest,
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RtioDestinationStatusRequest { destination: u8 },
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RtioDestinationStatusReply { up: bool },
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DmaRecordStart(&'a str),
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DmaRecordAppend(&'a [u8]),
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DmaRecordStop {
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duration: u64
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},
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DmaEraseRequest {
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name: &'a str
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},
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DmaRetrieveRequest {
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name: &'a str
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},
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DmaRetrieveReply {
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trace: Option<&'a [u8]>,
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duration: u64
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},
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RunFinished,
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RunException {
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exceptions: &'a [Option<eh::eh_artiq::Exception<'a>>],
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stack_pointers: &'a [eh::eh_artiq::StackPointerBacktrace],
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backtrace: &'a [(usize, usize)]
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},
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RunAborted,
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RpcSend {
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async: bool,
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service: u32,
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tag: &'a [u8],
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data: *const *const ()
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},
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RpcRecvRequest(*mut ()),
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RpcRecvReply(Result<usize, eh::eh_artiq::Exception<'a>>),
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RpcFlush,
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CacheGetRequest { key: &'a str },
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CacheGetReply { value: &'static [i32] },
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CachePutRequest { key: &'a str, value: &'a [i32] },
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CachePutReply { succeeded: bool },
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I2cStartRequest { busno: u32 },
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I2cRestartRequest { busno: u32 },
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I2cStopRequest { busno: u32 },
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I2cWriteRequest { busno: u32, data: u8 },
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I2cWriteReply { succeeded: bool, ack: bool },
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I2cReadRequest { busno: u32, ack: bool },
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I2cReadReply { succeeded: bool, data: u8 },
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I2cBasicReply { succeeded: bool },
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I2cSwitchSelectRequest { busno: u32, address: u8, mask: u8 },
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SpiSetConfigRequest { busno: u32, flags: u8, length: u8, div: u8, cs: u8 },
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SpiWriteRequest { busno: u32, data: u32 },
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SpiReadRequest { busno: u32 },
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SpiReadReply { succeeded: bool, data: u32 },
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SpiBasicReply { succeeded: bool },
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Log(fmt::Arguments<'a>),
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LogSlice(&'a str)
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}
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pub use self::Message::*;
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